A. Oishi

Stress controlled shallow trench isolation technology to suppress the novel anti-isotropic impurity diffusion for 45nm-node high-performance CMOSFETs

The most suitable STI filling process has been developed for 45nm-node SoC platform. We found that the stress induced anti-isotropic impurity diffusion, which causes the Vth lowering. This novel phenomenon has been controlled by optimizing the SOD/HDP-CVD hybrid STI filling structure. At the same time, 20% drive current improvements of nFET and pFET have been obtained.

Mobility improvement for 45nm node by combination of optimized stress and channel orientation design

Performance improvement of CMOSFET by adopting <100>-channel direction with high tensile stress gate capping layer (GC liner-SiN) was demonstrated. For pMOSFET, higher hole mobility of <100>-channel and lesser short channel effect (SCE) results in 20% improvement of I/sub on/. In addition, this improvement was not sensitive to local uniaxial strain. For nMOSFET, similar to <110>-channel, 10% improvement of I/sub on/ is realized in <100>-channel with high tensile stress gate capping layer. Thus, this technology can improve the performance of nMOSFET and pMOSFET without introducing specific additional processes for nMOSFET and pMOSFET.

High performance CMOSFET technology for 45nm generation and scalability of stress-induced mobility enhancement technique

High performance CMOSFET technology for 45nm generation is demonstrated. The key device strategies for junction scaling, gate stack scaling and stress-induced mobility enhancement are discussed. Reversed-order junction formation improves short channel effect (SCE) drastically. Novel SiON with improved poly-Si gate depletion improves the drive current by 8%. The systematic study on the process-induced mobility enhancement is performed and it is confirmed that the new scheme such as eSiGe and stress liner techniques are suitable for 45nm technology CMOSFET. It is confirmed that the stress enhancement factors using multiple booster techniques remain valid, which proves that these techniques are scalable for future technology

Impact of parasitic resistance and silicon layer thickness scaling for strained-silicon MOSFETs on relaxed Si/sub 1-x/Ge/sub x/ virtual substrate

This paper discusses the root causes of the fact that only slight performance improvement of MOSFET with strained-Si substrate has been achieved in short channel region (L < 100 nm). The performance improvement in short channel region is found to deteriorate mainly due to the parasitic resistance increase and tensile stress relaxation in the strained-Si layer. In regard to the parasitic resistance and the stress relaxation in small device geometry, the scaling impacts of strained-Si layer thickness (T/sub ss/) are investigated from the viewpoint of both DC and AC characteristics. Within this work, T/sub ss/ reduction down to 5 nm improves the current drive (I/sub d/) of nFET up to 6 % (L < 50 nm) compared with conventional bulk nFET. Propagation delay time (/spl tau//sub pd/) improvement in CMOS inverter is also observed to be more than 15 %. Finally, the impurity profile optimization is proposed to improve MOSFET performance toward the 45 nm node CMOS era.

Scalability of strained silicon CMOSFET and high drive current enhancement in the 40 nm gate length technology

In this work, we investigated the scalability of strained Si technology. The impact of scaling source/drain length (L/sub SD/) on electrical characteristics was studied for the first time. Drive current enhancement of strained PMOSFET usually disappears as L/sub SD/ is scaled down due to the stress induced by shallow trench isolation (STI). However, it is demonstrated that with an optimized fabrication process, PMOSFET drive current can be improved by 11% for a feature size of 40 nm gate length and small L/sub SD/ (240 nm). In addition, ring oscillator propagation delay is improved by 18%, which clearly supports the scalability of strained Si devices for future LSI.

A high performance 100 nm generation SOC technology (CMOS IV) for high density embedded memory and mixed signal LSIs

This paper demonstrates a 100 nm generation SOC technology (CMOS IV) for the first time. Three types of core devices are presented with optimized gate oxynitrides for their stand-by power conditions. This advanced logic process is compatible with 0.18 /spl mu/m/sup 2/ trench capacitor DRAM and 1.25 /spl mu/m/sup 2/ 6 transistor SRAM. Two kinds of high V/sub dd/ devices can be prepared by the triple gate oxide process. Moreover, for mixed signal applications, Ta/sub 2/O/sub 5/ MIM capacitors are introduced into Cu and low-k interconnects.

A 45nm High Performance Bulk Logic Platform Technology (CMOS6) using Ultra High NA(1.07) Immersion Lithography with Hybrid Dual-Damascene Structure and Porous Low-k BEOL

We present the state-of-the-art 45nm high performance bulk logic platform technology which utilizes, for the first time in the industry, ultra high NA (1.07) immersion lithography to realize highly down-scaled chip size. Fully renovated MOSFET integration scheme which features reversed extension and SD diffusion formation is established to meet Vt roll-off requirement with excellent transistor performance of Ion=1100muA/mum for nFET and Ion=700muA/mum for pFET at Ioff=100nA/mum. Also, we achieved excellent BEOL reliability and manufacturability by implementing hybrid dual-damascene (DD) structure with porous low-k film (keff=2.7)

45nm CMOS platform technology (CMOS6) with high density embedded memories

This paper describes the first 45nm Node CMOS technology (CMOS6) with optimized Vdd, EOT and BEOL parameters. For this technology to be applicable from high performance CPU to mobile applications, three sets of core devices are presented which are compatible with 0.069um/sup 2/ trench capacitor DRAM and 0.247um/sup 2/ 6Tr.SRAM embedded memories.

Scalable eSiGe S/D Technology with Less Layout Dependence for 45-nm Generation

We developed a less layout-dependent epitaxially grown SiGe (eSiGe) source/drain (S/D) technique for pFET. We found that the effective stressor region of eSiGe existed only near the channel and that the volume effect of eSiGe was small. On the basis of this mechanism, a new recess RIE and a new epitaxial growth technology were developed, so that the gate-pitch dependence, S/D length dependence and channel width dependence were extremely reduced. In addition, we succeeded in increasing the drive current by improving the eSiGe structure and the impurity profile. We also obtained a high drive current of 750 muA/mum at Vdd=1V, Ioff=100nA/mum

High density and fully compatible embedded DRAM cell with 45nm CMOS technology (CMOS6)

For the first time, a deep trench based embedded DRAM cell for 45nm node system on a chip (SoC) applications is presented. We achieve both high data retention time and full compatibility with logic process, while scaling eDRAM cell down to 0.069/spl mu/m/sup 2/ size. In order to compensate the loss of capacitance in aggressively scaled deep trench, high enhancement of storage node capacitance up to 60% is achieved by introducing the bottle etching process with LOCOS collar structure and the high-k node dielectric material (Al/sub 2/O/sub 3/). Hybrid STI structure is applied for void free gap filling, and high improvement of retention time is obtained by reduction of induced stress. Ultra shallow buried strap (USBS) structure without silicide block process realizes the integration without any extra process after deep trench formation and extremely low strap resistance. No degradation of retention characteristics is observed by introducing Ni silicide on the top of storage node junction. Disposable sidewall spacer and flash lamp anneal, which are key technologies of logic transistor, are also applied to eDRAM cell successfully. In addition, high functional test yield up to 61 % has been obtained for 256Kb ADM.