H. Yoshimura

Advanced DSS MOSFET technology for ultrahigh performance applications

Dopant segregated Schottky MOSFET (DSS FET) is one of the key technologies which can improve the MOSFET performance thanks to reduction of external resistance and increase of carrier injection velocity. We have found that both laser spike annealing (LSA) and fluorine co-implant can reduce external resistance furthermore, which leads to boost drive currents of DSS FETs by 7% respectively. By optimizing these technologies, high drive currents of 1310 muA/mum and 1080 muA/mum at Ioff of 100 nA/mum are achieved at 1.0 V and 0.9 V respectively, without use of high-k/metal gate.

Monte Carlo simulation and measurement of nanoscale n-MOSFETs

The output characteristics of state-of-the-art n-MOSFETs with effective channel lengths of 40 and 60 nm have been measured and compared with full-band Monte Carlo simulations. The device structures are obtained by process simulation based on comprehensive secondary ion mass spectroscopy and capacitance-voltage measurements. Good agreement between the measured output characteristics and the full-band Monte Carlo simulations is found without any fitting of parameters and the on-currents are reproduced within 4%. The analysis of the velocity profiles along the channel confirms that the on-current is determined by the drift velocity in the source side of the channel. Analytic-band Monte Carlo simulations are found to involve an overestimation of the drain current in the nonlinear regime which becomes larger for increasing drain voltage and decreasing gate length. The discrepancy originates from a higher nonlinear drift velocity and a higher overshoot peak in bulk silicon which is due to differences in the band structures above 100 meV. The comparison between analytic-band and full-band Monte Carlo simulation therefore shows that the source-side velocity in the on-state is influenced by nonlinear and quasiballistic transport.

Variability aware modeling and characterization in standard cell in 45 nm CMOS with stress enhancement technique

Gate density is ultimately increased to 2100 kGates/mm2 by pushing the critical design rules without increasing the circuit margin in 45 nm technology. Layout dependences for stress enhanced MOSFET including contact positioning, 2nd neighboring poly effect, and bent diffusion are accurately modeled for the first time. With the constructed design flow, gate length change of -2.8% to +3.6% and Idsat change of -10% to +14% are removed from uncertain margin in 45 nm corner libraries.

Layout Dependence Modeling for 45-nm CMOS With Stress-Enhanced Technique

Layout dependences for stress-enhanced MOSFETs including contact positioning, the second neighboring poly effect, and bent diffusion are modeled in 45-nm CMOS logic technology. It is found that the sensitivity of contact position in the channel direction is larger for PMOS with a higher stress liner than for NMOS. The effect of contact positions is modeled by using the distance of contact to gate (x) and the number of contacts (N). In terms of the gate-space effect, it is concluded that, in addition to the neighboring gates, second neighboring gates affect the channel stress. The effect of bent-shape diffusion is analyzed for NMOS and PMOS. For NMOS, the channel profile is affected by the bent shape. This can be described by the change of V th. For PMOS, the channel stress is modulated by the bent diffusion. The stress effect in bent-shape diffusion for PMOS is modeled with three geometrical parameters. The compact model is applied to the characterization of actual 45-nm cell libraries. It is confirmed that, with the constructed models and design flow, a saturation current (I dsat) change of -12%-14% is removed from the uncertain margin in 45-nm corner libraries.

Compact model for layout dependent variability

We have developed a compact model which deals with MOSFET characteristic variations arising from design layout dependences. It treats many stress related variations and their interactions that are especially important in 45 nm technology node. It is demonstrated that the model can predict MOSFET characteristics used in standard cells with high accuracy.

Comprehensive study on layout dependence of soft errors in CMOS latch circuits and its scaling trend for 65 nm technology node and beyond

Accelerated soft error testing with proton beam was performed for 65 nm CMOS latches for the first time. The soft-error rate (SER) dependence on the physical layout was clarified. SER has dependence on the size of the diffusion regions since critical charge and charge collection is strong function of them. By optimizing it, SER can be reduced by 70%. The scaling trend of SER was also investigated. It is shown that SER degradation due to scaling can be suppressed by the moderate reduction of the supply voltage.

An 80 nm dual-gate CMOS with shallow extensions formed after activation annealing and SALICIDE

Silicide compatible process flows for dual-gate CMOS with shallow extensions formed after activation annealing and Co SALICIDE (SEFAS) are proposed and adopted for 80 nm physical gate length CMOS. They show good DC and AC performances while keeping high reliability because of successful shallow extension formation. High f/sub T/ values of 80 GHz for NMOS and 47 GHz for PMOS are achieved.

Scaling scenario of multi-level interconnects for future CMOS LSI

Scaling guidelines for multi-level interconnects for future CMOS LSI are presented. They are based upon intensive circuit simulation combined with a 2D field solver while considering the wire length distribution of logic circuits. Interconnect structures such as metal aspect ratio and ILD thickness are optimized to minimize wiring delay without causing crosstalk problems. In addition, the scaling factors of future BEOL parameters are presented.

Quantitative full 3D blooming analysis on 1.4um BSI CMOS image sensor

3D TCAD analysis of blooming for 1.4 μm CMOS image sensor (CIS) with two-shared pixel structure has been performed. Its blooming behavior has been modeled and clear design guidelines for potential control inside CIS pixels have been obtained.

Suppression of NBTI-induced VMIN shifts using hafnium doping to gate poly/SiON interface and optimized NiPt process for 40nm node SRAM cell

Hafnium introduction to poly/SiON interface has been found effective to suppress the increase of minimum operating voltage (VMIN) caused by NBTI-induced VT shift in 40nm node low power SRAM. In addition, the distribution tail of N+ node junction leakage current has been identified as enhancing VMIN failure due to NBTI, and has been improved by optimizing NiPt silicide process. Finally operation of 32Mbit 0.24µm2 low power SRAM with VMIN less than 0.9V has been demonstrated.