T. Noguchi

Stress controlled shallow trench isolation technology to suppress the novel anti-isotropic impurity diffusion for 45nm-node high-performance CMOSFETs

The most suitable STI filling process has been developed for 45nm-node SoC platform. We found that the stress induced anti-isotropic impurity diffusion, which causes the Vth lowering. This novel phenomenon has been controlled by optimizing the SOD/HDP-CVD hybrid STI filling structure. At the same time, 20% drive current improvements of nFET and pFET have been obtained.

Mobility improvement for 45nm node by combination of optimized stress and channel orientation design

Performance improvement of CMOSFET by adopting <100>-channel direction with high tensile stress gate capping layer (GC liner-SiN) was demonstrated. For pMOSFET, higher hole mobility of <100>-channel and lesser short channel effect (SCE) results in 20% improvement of I/sub on/. In addition, this improvement was not sensitive to local uniaxial strain. For nMOSFET, similar to <110>-channel, 10% improvement of I/sub on/ is realized in <100>-channel with high tensile stress gate capping layer. Thus, this technology can improve the performance of nMOSFET and pMOSFET without introducing specific additional processes for nMOSFET and pMOSFET.

Scalability of strained silicon CMOSFET and high drive current enhancement in the 40 nm gate length technology

In this work, we investigated the scalability of strained Si technology. The impact of scaling source/drain length (L/sub SD/) on electrical characteristics was studied for the first time. Drive current enhancement of strained PMOSFET usually disappears as L/sub SD/ is scaled down due to the stress induced by shallow trench isolation (STI). However, it is demonstrated that with an optimized fabrication process, PMOSFET drive current can be improved by 11% for a feature size of 40 nm gate length and small L/sub SD/ (240 nm). In addition, ring oscillator propagation delay is improved by 18%, which clearly supports the scalability of strained Si devices for future LSI.

Relief of hot carrier constraint on submicron CMOS devices by use of a buried channel structure

Hot carrier effects of submicron buried channel NMOS devices with a LDD structure have been investigated because of a need to realize high performance future VLSI structure. The stress experiments show that the buried channel device is resistant to hot carrier effects and give a relief of hot carrier constraint for the scaled down devices. The improvement in hot carrier degradation is attributed to the deeper and broader current path in the buried channel structure. Dependences of the hot carrier effect and the short channel effect on the channel junction depth are discussed. These results help select the most promising buried channel CMOS structure for high-speed and high-reliability future VLSI.

New guideline of Vdd and Vth scaling for 65nm technology and beyond

We show new guideline of Vdd and Vth scaling for logic blocks and high density SRAM cell from low power dissipation viewpoint. New degradation mode for inverter delay becomes major obstacle for Vdd scaling in the future. Low Vdd and low Vth should be applied only for circuits with high switching activity. In other portions, Vdd should be kept around 1-1.2V. High density SRAM with beta ratio of 1(0.56 /spl mu/m/sup 2/) operates at 0.7V by choosing optimum Vth.

45nm CMOS platform technology (CMOS6) with high density embedded memories

This paper describes the first 45nm Node CMOS technology (CMOS6) with optimized Vdd, EOT and BEOL parameters. For this technology to be applicable from high performance CPU to mobile applications, three sets of core devices are presented which are compatible with 0.069um/sup 2/ trench capacitor DRAM and 0.247um/sup 2/ 6Tr.SRAM embedded memories.

High performance 30 nm bulk CMOS for 65 nm technology node (CMOS5)

In this paper, we demonstrate high performance CMOS devices developed for the 65 nm technology node. The gate length is shrunk down to 30 nm. The gate oxide is nitrided oxide of 1 nm EOT with an abrupt nitrogen profile. In order to satisfy both the high activation of the gate polysilicon and suppression of the short channel effect, we applied high dose PMOS doping and low temperature spike anneal to the source and drain. Junction leakage is suppressed by applying nickel silicide in such shallow deep junctions. At a supply voltage of 0.85 V, high drive currents (700 /spl mu/A//spl mu/m at Ioff=100 nA//spl mu/m for nMOSFET and 300 /spl mu/A//spl mu/m at Ioff=100 nA//spl mu/m for pMOSFET) and low CV/I values (0.71 ps at Ioff=100 nA//spl mu/m for nMOSFET and 1.41 ps at Ioff=100 nA//spl mu/m for pMOSFET) are achieved. They are the best among published data.

Comprehensive study on layout dependence of soft errors in CMOS latch circuits and its scaling trend for 65 nm technology node and beyond

Accelerated soft error testing with proton beam was performed for 65 nm CMOS latches for the first time. The soft-error rate (SER) dependence on the physical layout was clarified. SER has dependence on the size of the diffusion regions since critical charge and charge collection is strong function of them. By optimizing it, SER can be reduced by 70%. The scaling trend of SER was also investigated. It is shown that SER degradation due to scaling can be suppressed by the moderate reduction of the supply voltage.

New considerations for highly reliable PMOSFETs in 100 nm generation and beyond

The hot-carrier (HC) instability for surface channel PMOSFETs is investigated intensively. We found from experimental data that hot-carrier injection occurs at the channel center under the most serious stress condition of V/sub gs/=V/sub ds/ and that a physical mechanism similar to NBTI is responsible for degradation at room temperature, and confirmed from hydrodynamic simulations. We demonstrate that mechanical stress resulting from the sidewall spacer accelerates this anomalous degradation in short-channel PMOS under hot-carrier stress. We show that management of this degradation mechanism is indispensable for achieving high reliability in future generation PMOS devices.

High density and fully compatible embedded DRAM cell with 45nm CMOS technology (CMOS6)

For the first time, a deep trench based embedded DRAM cell for 45nm node system on a chip (SoC) applications is presented. We achieve both high data retention time and full compatibility with logic process, while scaling eDRAM cell down to 0.069/spl mu/m/sup 2/ size. In order to compensate the loss of capacitance in aggressively scaled deep trench, high enhancement of storage node capacitance up to 60% is achieved by introducing the bottle etching process with LOCOS collar structure and the high-k node dielectric material (Al/sub 2/O/sub 3/). Hybrid STI structure is applied for void free gap filling, and high improvement of retention time is obtained by reduction of induced stress. Ultra shallow buried strap (USBS) structure without silicide block process realizes the integration without any extra process after deep trench formation and extremely low strap resistance. No degradation of retention characteristics is observed by introducing Ni silicide on the top of storage node junction. Disposable sidewall spacer and flash lamp anneal, which are key technologies of logic transistor, are also applied to eDRAM cell successfully. In addition, high functional test yield up to 61 % has been obtained for 256Kb ADM.