A. P. Dorey

Reliability testing by precise electrical measurement

Tests have been devised which provide indication of incipient failure of CMOS devices. The experimental methodology to confirm the value of the tests depends on the acceptance of the Arrenhius relationships as it was investigated using accelerated life test techniques. Tests have included leakage current, transient current, electrical noise, upper cutoff frequency and delay times. The devices under tests have been stressed to accelerate aging and the results of the diagnostic electrical measurements correlated with subsequent failure. Consideration has been given to the implementation of the reliability tests in conjunction with the normal functional testing.<<ETX>>

A fault simulation methodology for MEMS

Efficient built-in and external test strategies are becoming essential in microelectromechanical systems (MEMS), especially for high reliability and safety critical applications. To be realistic however, internal and external test must be properly validated in terms of fault coverage. Fault simulation is hence likely to become a critical utility within the design flow. This paper discuss methods for achieving test support based on the extension of tools and techniques currently being introduced into the mixed signal ASIC market.

Finite element analysis to support component level fault modeling for MEMS

Component level (nodal) simulations have been proposed to both implement closed loop simulation of complete microsystems to support the migration to shorter design cycles and implement fault models of micro-mechanical components. Within such a simulation environment, library cells in the form of behavioral models, are used for the basic components of microelectromechanical (MEM) transducers, such as beams, plates, comb-drives and membranes. This paper presents both a methodology to generate the model parameters required for the implementation of accurate component level fault models and simulation results from a number of representative defective structures in a MEMS product.

Assessment of the Tests as Predictors of Failure

In this section we will illustrate the usefulness of the devised tests by referring to the behavior of the devices subject to thermal and electrical stress. Before we discuss this in detail in the next few subsections we first of all introduce the experimental details for reference.

Implementation of the Tests for Industrial Use

In the preceding chapters a series of analog tests have been described which can be performed on digital ICs to assess their quality of manufacture and hence their probable lifetime in use. The description has concentrated on the tests themselves, the way in which they are performed, their sensitivity, their ability to detect weak devices and a justification for supposing that the test results actually produce a measure of the quality of the device. The development of the tests, their assessment and their verification in sample batches of stressed devices has been carried out under laboratory conditions such that the basis of the tests is fully understood. The results suggested strongly that for the CMOS family studied, the tests can be a valuable set of laboratory procedures.

Introduction to VLSI Testing

Digital, very large scale integrated circuits (VLSICs) are used widely. In many applications the incorrect function of the circuit upon installation, or the malfunction or failure during use, are inconveniences which are often detected during the early operation or burn-in period of the system in which the circuit is used. However, in some applications where the replacement cost is high or the consequences of failure are serious, highly reliable devices of high quality are needed. Examples of such uses are in satellites, undersea cable, remote stations, manned space vehicles and for military systems.

The Devices Studied and their Simulation

As part of the general investigation of rapid reliability assessment the devices being studied experimentally were also simulated using a standard circuit simulation package, PSPICE (Microsim Corporation), which i3 a version written for use on the IBM personal computer. The simulations gave the size and shape of the waveforms occuring in the circuits being studied and the effect of different conditions within the circuit on these waveforms.

The Tests and Stress Experiments

As has been discussed in Chapter 1 there are, in general, two types of approaches toward reliability testing of digital ICs. Digital testing, which is the conventional approach, is normally developed on the basis of the function that the device is supposed to perform. The criterion for this approach is then function or malfunction. The problem is therefore transformed into mathematical operations which are tackled with the help of computer-aided design (CAD) techniques. This approach ignores the detail of the failure modes which involves a separate detailed analysis of the devices by experiment. The other approach is derived from the parametric characteristics such as supply current, threshold voltage, propagation delay, cut-off frequency, and so on, which are normally analog features. Instead of being functionally related and digital as in digital testing, this approach detects gradual changes or degradation of the electrical parameters which may not be large enough to cause a complete functional fault at that moment. These parameters are closely related to the chemical and physical processes of the operating devices and affect the performance of the device in one way or another. In developing test methods for this approach, the tactics involved in the development of digital testing are no longer valid since the target is now to measure gradual changes or degradation of the parameters, not necessarily the digital fault.