A. Lechner

A design for testability study on a high performance automatic gain control circuit

A comprehensive testability study on a commercial automatic gain control circuit is presented which aims to identify design for testability (DfT) modifications to both reduce production test cost and improve test quality. A fault simulation strategy based on layout extracted faults has been used to support the study. The paper proposes a number of DfT modifications at the layout, schematic and system levels together with testability. Guidelines that may well have generic applicability. Proposals for using the modifications to achieve partial self test are made and estimates of achieved fault coverage and quality levels presented.

Design for testability strategies for mixed signal & analogue designs-from layout to system

The cost and complexity of mixed signal and analogue production test programs is lending to considerable interest in Design for testability (DfT) techniques that have the potential to improve testability by reducing implementation cost and improving outgoing quality. These techniques range from rules and guidelines for schematic and physical design to full built-in-self-test (BIST) solutions. This paper presents a summary of a number of possible DfT approaches that may well help to solve test cost and test quality difficulties for analogue and mixed signal integrated circuits.

A digital partial built-in self-test structure for a high performance automatic gain control circuit

it is now widely recognised that design-for-testability and built-in self-test techniques will be mandatory to meet test and quality specifications in next generation mixed signal integrated systems. This paper describes a new digital on-chip post processing function capable of reducing production test time for a high performance automatic gain control circuit by 70%.

Towards a better understanding of failure modes and test requirements of ADCs

It is now widely recognised that Built-in Self-Test (BIST) techniques and Design-for-Testability (DfT) will be mandatory to meet test and quality specifications in next generation mixed signal ICs. For evaluating, verifying, and comparing testability improvements, a more detailed understanding of circuit specific failure modes is essential. This paper presents fault simulation results for a 6-bit ADC and identifies typical failure modes the converter is likely to exhibit and hence must be tested for.

Test of A/D Converters

Converter testing is a complex process. Test specifications are application dependent and in most cases require sophisticated stimulus generation and, response analysis equipment. The processing of sampled data to generate specification measurements also requires complex DSP algorithms. Furthermore, test complexity increases with speed, resolution and technology advances. This chapter summaries the key test specifications, conventional methods of verifying these specifications and potential built-in self-test solutions.

Short circuit faults in state-of-the-art ADCs - are they hard or soft?

For next generation deep sub-micron (DSM) analogue and mixed signal ICs, the integration of Design-for-Test (DfT), Design for-Manufacturability (DfM), Defect-Oriented Test (DOT) approaches, and Built-In Self-Test (BIST) techniques into the design and manufacturing cycle will gain increasing importance to the context of implementing a structural IC test methodology (1). This paper discusses the relevance of fault simulation techniques to investigate realistic circuit failure modes and test requirements. It is shown for an ADC target design that hard faults frequently cause marginal rather than catastrophic failure, hence have to be subject to test.

Investigation into the Use of Hybrid Solutions for ΣΔ A/D Converter Testing

AbstractΣΔ ADCs are now extensively used in electronic system applications requiring high resolution analogue to digital interfaces. Many of these applications require low cost solutions that imply the need for efficient production test strategies for verifying performance specifications. Industrial state-of-the-art is based on DSP testing to extract dynamic performance such as THD and SNR from an FFT on a sampled bit-stream from the decimator output. This method is computationally expensive and as resolution increases, the total number of samples required also increases thus pushing total test time beyond acceptable limits. This paper proposes an alternative hybrid solution based on an initial low-cost wafer level screening test followed by a DSP based technique on marginal devices based on alternative DSP transforms. The screening test is applied to the high-frequency bit-stream output of the ΣΔ modulator and has potential for on-chip implementation. Relatively simple algorithms and cross-correlation techniques are used that can associate specific changes in the bit-stream pattern to key failure modes affecting dynamic performance parameters. A simplified supplementary DSP test for marginal devices is proposed that is less computationally intensive than FFT analysis.