K.T. Ng

Substrate effects in monolithic RF transformers on silicon

The effect of substrate RF losses on the characteristics of silicon-based integrated transformers is studied experimentally by using a substrate transfer technique. The maximum available gain is used to evaluate the quality of transformers similarly to that of active devices. The silicon substrate has a pronounced effect on the quality factor and mutual resistive coupling factor of the primary and secondary coils, thereby degrading the maximum available gain of the transformer. A highly structured patterned ground shield is shown to improve the maximum available gain of a transformer at high frequencies, while at low frequencies, it has little effect on the maximum available gain and even degrades the quality factors of the transformer coils. It is shown that the low-frequency degradation of the coil quality factors relates to local eddy currents in the patterned metal shield.

IC-compatible two-level bulk micromachining process module for RF silicon technology

This paper presents a novel two-level silicon bulk micromachining for integration of RF devices. The RF devices are fabricated at the frontside of Si(100) wafers using conventional IC technology. A post-processing module is applied from the wafer backside with precise alignment to the frontside. This module can provide a blanket ground plane at an optimum position beneath the wafer surface, a frontside contact from the wafer surface to that ground plane, and trenches to suppress crosstalk through the conductive silicon by adding two mask levels. An extension to four masks allows for an integration of large passive components beneath circuitry for a much reduced chip area, lowering chip size and cost. The feasibility of the novel post-process module is demonstrated through the fabrication of microstrip transmission lines, conductor-backed spiral inductors, trench-barriers against crosstalk through the conductive silicon substrate, and high-quality subsurface spiral inductors.

A micromachining post-process module for RF silicon technology

A bulk-micromachining post-process module, based on two-level structuring of RF silicon substrates and a 4-/spl mu/m thick one-level sub-surface metal pattern, is presented. This allows for fabricating three-dimensional structures for novel RF components and has potential in more compact integration. Next to a concise description of the relevant aspects of the fabrication process, mechanical stability of the postprocessed wafers is analyzed. Sub-surface spiral inductors with good quality and low coupling to inductors built at the wafer surface are presented, thus demonstrating the feasibility of three-dimensional integration of RF components.

Substrate options and add-on process modules for monolithic RF silicon technology

Add-on process modules as enhancements of standard high-frequency silicon integration processes are discussed. Such modules can be added without any interference with the core process before (pre-process modules), during (mid-process modules), or after (post-process modules) the circuit integration. High-resistivity silicon substrates, the patterned metal ground shield, and bulk micromachining are presented as examples in each category, respectively.

Characterization of a bulk-micromachined post-process module: for silicon RF technology

In spite of the many advantages of state-of-the-art silicon technology, the lack of a RF ground plane at sufficient distance beneath the surface and the frontside contact to it are likely to present considerable shortcomings for future radiofrequency (RF) applications. Further, the RF crosstalk through the conductive silicon substrate cannot easily be minimized. By the local removal of the substrate-silicon, the crosstalk and loss can largely be reduced. In order to overcome these shortcomings, a novel post-processing technology, applicable to any industrial integration process, is proposed and characterized in this paper.

IC-Compatible Two-level Bulk Micromachining for RF Silicon Technology

This paper presents a novel two-level silicon bulk micromachining for integration of RF (radio frequency) devices. The RF devices are fabricated at the frontside of Si (100) wafers using conventional IC technology. A post-processing module is applied from the wafer backside. This module provides a blanket ground plane at an optimum position beneath the wafer surface, a front-side contact from the wafer surface to that ground plane and trenches to suppress cross talk through the conductive silicon. Moreover, due to the front-side RF ground contact, compatibility to conventional packaging is maintained. The feasibility of the new postprocess module is demonstrated through the fabrication of microstrip transmission lines and conductor-backed spiral inductors.

Through-Wafer Copper Electroplating for RF Silicon Technology

Silicon micromachining techniques are powerful tools to realize three-dimensional (3D) structures thus allowing a more compact-integration of RF components in silicon. In this paper a new approach consisting of deep vertical through-wafer vias and copper metallization for RF silicon integration is introduced. A novel technique to fill the dry etched, high-aspect ratio, closely spaced vias is presented. Vias as small as 5 μm in diameter and with an aspect ratio of more than 10 are filled completely by copper electroplating without any void or defect. The fabrication process and the electrical characterization of the through-wafer Cu plugs are presented. Several novel RF structures with throughwafer connections are realized successfully using the technique developed.

Integrated RF passive components - discrete vs. distributed

Passive components have been recognized as performance as well as cost limiting elements of integrated radio-frequency (RF) systems. While the integration of high-quality capacitors at small area appears feasible, those requirements are not easily met for inductors. The frequency range, at which discrete spiral inductors can efficiently be used, is limited at around 1 GHz by size and at about 15 GHz by the controllable minimum inductance value. Distributed networks on silicon substrates appear feasible for frequencies above 35 GHz, at which the length of a /spl lambda//4-transmission line becomes smaller than 1 mm. In the intermediate frequency range from 15 GHz to 35 GHz neither discretes nor distributed elements can easily be applied. Here, periodic structures, consisting of discrete components and transmission line sections and operating in slow-wave mode, can provide practical solutions.

Integrated Transmission Lines on High-Resistivity Silicon: Coplanar Waveguides or Microstrips?

We present an experimental study of the effect of the accumulation or inversion layer at the surface of a high-resistivity silicon substrate on the loss of transmission lines. It is shown that the relative contribution of the surface channel to the total loss becomes increasingly significant as the silicon resistivity decreases. The experiments demonstrate that the effect of the surface channel on the loss of an integrated microstrip is considerably lower than that of a comparable coplanar waveguide, favoring microstrips for integration on high-resistivity silicon substrates.

A sub-surface metallization post-process IC module for RF technology

A novel post-process bulk-micromachining module for sub-surface metallization is presented. The module provides an integrated radio-frequency (RF) ground plane at sufficient distance beneath the wafer surface and a frontside contact to that ground plane to integrate conductor-backed inductors and microstrips, as well as a trench structure for crosstalk suppression in RF circuits.