A. Popescu

Breakdown analysis in JI, SOI and partial SOI power structures

Summary form only given. SOI could be the future technology for power devices and integrated circuits. Unlike the conventional Junction Isolation (JI) technology, SOI benefits from simple and effective isolation, low leakage currents, reduced interference between low voltage and high voltage components and very high speed. SOI may, however, suffer from low breakdown voltage, self-heating and latch-up. These are essential aspects, especially for high power applications, where high currents and high voltages are required. The key issue in building a Power Integrated Circuit (PIC) based on SOI is an efficient Resurf (REduced SURface Field) effect to ensure a high breakdown voltage. This may be achieved by using a thick oxide layer and a top field oxide. However, thick oxide layers may cause high temperatures to be developed in the circuit. At the same time the final breakdown voltage is still below that of an optimised JI structure. New partial SOI device structures are proposed and demonstrated through numerical simulations. It is shown that the partial SOI technology solves one of the major problems of conventional SOI technology, the reduced breakdown voltage, with little compromise in the switching speed and device isolation. Extensive two-dimensional analyses and analytical modelling of the breakdown behaviour in JI, SOI and partial SOI have been carried out. The results indicate that partial SOI technology could be a serious alternative to conventional SOI for PICs.

Silicon-on-insulator power integrated circuits

A power integrated circuit process has been developed, based on silicon-on-insulator, which allows intelligent CMOS control circuitry to be placed alongside integrated high-voltage power devices. A breakdown voltage of 335 V has been obtained by using a silicon layer of 4 μm thickness together with a buried oxide layer of 3 μm thickness. The respective LDMOS specific on-resistance and LIGBT on-state voltage for this breakdown voltage were 148 mΩ cm2 and 3.9 V, respectively.

The 3D RESURF junction

This paper reports a new device concept-the 3D RESURF junction, which is applicable to a large class of power devices which we term 3D power devices. The new class of devices features considerably superior breakdown performance compared to any lateral power devices reported to date and challenges the state-of-the art vertical devices such as the VDMOSFET. The 3D Double Gate devices also benefit by having a low on-resistance due to carrier modulation in the drift region. The 3D RESURF is demonstrated numerically through extensive, advanced 2-D and 3-D simulations.

A new class of lateral power devices for HVIC's based on the 3D RESURF concept

This paper reports a new device concept applicable to a large class of power devices which we term 3D power devices. The concept is based on 3D fundamental forward blocking and 3D on-state operation using a transversal junction perpendicular on the axis between the main terminals. This junction acts effectively to spread uniformly the potential in the blocking mode and allows 3D minority injection across it in the on-state. Several devices are reported, and demonstrated through 2D Medici and 3D Davinci simulations.

Generalized parity measurements

Measurements play an important role in quantum computing (QC), by either providing the nonlinearity required for two-qubit gates (linear optics QC), or by implementing a quantum algorithm using single-qubit measurements on a highly entangled initial state (cluster state QC). Parity measurements can be used as building blocks for preparing arbitrary stabilizer states, and, together with 1-qubit gates are universal for quantum computing. Here we generalize parity gates by using a higher dimensional (qudit) ancilla. This enables us to go beyond the stabilizer/graph state formalism and prepare other types of multi-particle entangled states. The generalized parity module introduced here can prepare in one-shot, heralded by the outcome of the ancilla, a large class of entangled states, including GHZ_n, W_n, Dicke states D_{n,k}, and, more generally, certain sums of Dicke states, like G_n states used in secret sharing. For W_n states it provides an exponential gain compared to linear optics based methods.

Minority carrier injection across the 3D RESURF junction

In this paper we report a novel class of semiconductor devices termed 3D devices, based on the application of the RESURF concept to the the third dimension. For the first time we demonstrate devices based on pure three-dimensional on-state/blocking operation with the third-dimension junction acting to enhance the breakdown capability in the voltage blocking mode and provide conductivity modulation in the on-state. A brief discussion of the ideal substrate to enhance breakdown performance is also given.

A numerical study of the RESURF effect in bulk and SOI power devices

A numerical study of the two-dimensional distribution of the electric field in Junction Isolated (JI), Silicon on Insulator (SOI) and partial SOI power devices has been performed. The partial SOI lateral power devices, earlier proposed by us, overcome the breakdown problems associated with conventional SOI power devices, while still maintaining a high speed and low electrical interference with associated low voltage CMOS circuitry.

Failure mechanisms of SOI high-voltage LIGBTs and LDMOSes under unclamped inductive switching

This paper examines the behaviour of silicon-on-insulator (SOI) LIGBTs and LDMOSes under unclamped inductive switching (UIS). Surprisingly, it is found that LIGBTs can absorb much less UIS current than LDMOSes, specifically only between one-half and one-third. Two-dimensional device simulation showed that this was because hole injection from the LIGBT anode during turn-off changed the potential distribution within the device, leading to field concentration beneath the gate and hence premature failure of the gate. This has an important impact on the choice of a power device in a power integrated circuit, and its design.

Quantum computation with ballistic qubits

We give a brief introduction to quantum computation and we discuss a possible solid state implementation. We show how to prepare and measure qubit states and how to implement single and 2-qubit gates with ballistic electrons.

Thin Partial SOI Power Devices for High Voltage Integrated Circuits

The forward blocking characteristics of lateral SOI power devices on a very thin (≤ 0.5 ¼m) silicon layer are analysed. It is known that SOI power devices suffer from reduced breakdown voltage due to the less efficient RESURF effect. Partial SOI technology results in a higher breakdown capability. In addition, partial SOI devices do not require the drift region to be linearly graded. Moreover, the self-heating effect in partial SOI devices is drastically reduced since the patterned oxide layer is very thin and heat can dissipate via the silicon window to the substrate, which also helps to distribute the temperature more evenly in the drift region. It is concluded that thin partial SOI power devices could be strong candidates for high voltage ICs (HVICs).