D.M. Garner

Ultra-fast LIGBTs and superjunction devices in membrane technology

Back-side etching of the entire silicon substrate under part of the drift region of a SOI power device was first proposed by Udrea and Amararunga (2004) and experimentally reported by Udrea et al. (2005). This technology concept enables high voltage devices to be embedded in a thin silicon/oxide membrane resulting in very significant improvements in breakdown ability and switching speed. This paper presents new results from advanced membrane high power devices and fully functional power ICs. Furthermore, record switching speeds for the LIGBT are reported. The feasibility of realising superjunction structures (3D Resurf) with breakdown capability in excess of 700V using this technology are also demonstrated

Modelling of self-heating effect in thin SOI and Partial SOI LDMOS power devices

Abstract This paper presents a comprehensive 2-D and 1-D study of the self-heating effect in thin Silicon-on-Insulator (SOI) and Partial SOI LDMOS power devices. A simple 1-D self-heating model based on a PSPICE RC thermal circuit which accounts for the temperature rise in on-state, transient and short-circuit conditions is developed. Unlike previous 1-D modelling attempts for SOI devices, our model takes into account the feedback effect of the local device temperature on the thermal conductivity and specific heat through an equivalent electrical RC network consisting of voltage controlled resistors and capacitors. The 1-D model is thoroughly assessed against extensive 2-D thermal simulations performed using the SILVACO-ATLAS device simulator and the results indicate an excellent agreement in all operating conditions. Furthermore, an accurate comparison between the thin SOI and Partial SOI devices is carried out.

Silicon-on-insulator power integrated circuits

A power integrated circuit process has been developed, based on silicon-on-insulator, which allows intelligent CMOS control circuitry to be placed alongside integrated high-voltage power devices. A breakdown voltage of 335 V has been obtained by using a silicon layer of 4 μm thickness together with a buried oxide layer of 3 μm thickness. The respective LDMOS specific on-resistance and LIGBT on-state voltage for this breakdown voltage were 148 mΩ cm2 and 3.9 V, respectively.

Partial SOI LDMOSFETs for high-side switching

This paper describes the switching characteristics of Partial SOI LDMOSFETs in high-side configuration based on the results of numerical simulations. The effects of the substrate bias on the on-state and output capacitances of a device on a Partial SOI substrate are discussed and compared to a conventional SOI substrate. It is shown that having the Partial SOI LDMOSFETs operating in source-high conditions will help to achieve a faster turn-off due to reduced parasitic capacitances. In addition, it is shown that the turn-off speed of Partial SOI LDMOSFETs is at least 3 times higher than of conventional SOI LDMOSFETs.

Field-emission triodes with integrated anodes

A silicon microtriode where the gate and anode are fully integrated along with the cathode tip on the silicon substrate is proposed. The device can operate in two modes: a normally on mode and a normally off mode. In the normally on mode, reported here, the anode is a suspended bimetallic layer of chromium and gold above a sharp silicon tip, formed by the anisotropic etching of silicon in potassium hydroxide solution. The gate, in the same plane as the anode, is formed of the same bimetallic layer and approaches from the sides. The process requires only one mask and is extremely simple. Field emission was found between the anode and the cathode tip and, in three-terminal mode, the device was found to have gate control. The extrapolated gate pinch-off voltages for the two devices measured were −230 and −162 V at an anode voltage of 120 V.

The integration of high-side and low-side LIGBTs on partial silicon-on-insulator

Abstract Partial silicon-on-insulator (PSOI) is a new technology for fabricating power integrated circuits (PICs) in which the buried oxide is patterned to give silicon windows beneath the anodes of the power devices, yielding breakdown voltages and a self-heating effect comparable to those obtained in bulk silicon, yet while retaining the good isolation between the power devices and the low-power CMOS which is inherent in silicon-on-insulator [Popescu A, Udrea F, Milne W. Proceedings of CAS. 1997. p. 102–3; Lim H, Udrea F, Garner D, Milne W. Solid-State Electronics 1999;43(7):1267–80]. For a PIC, both a high-side and a low-side power device are often required. While this is possible when the power devices are LDMOSFETs [Lim H, Udrea D, Garner K, Shen K, Milne W. Proceedings of CAS. 1999. p. 149–52], high-side Lateral Insulated Gate Bipolar Transistors (LIGBTs) are difficult to fabricate in PSOI due to the unacceptably high leakage current which flows from the anodes of the LIGBTs, through the silicon window, to the substrate, and which can constitute 9.3% of the total device current. In this article, we present a novel method of eliminating that current by incorporating a deep n + diffusion between the anode of the high-side LIGBT and the silicon window. Therefore, a PSOI PIC technology is arrived at, which has everything that is required for a PIC technology: a high breakdown voltage, a similarly good self-heating effect to bulk technology, a good turn-off performance, good isolation between power devices and CMOS circuitry, and the availability of both high-side and low-side LIGBTs and LDMOSFETs.

An analytic model for turn off in the silicon-on-insulator LIGBT

Abstract Lateral insulated gate bipolar transistors (LIGBTs) in silicon-on-insulator (SOI) show a unique turn off characteristic when compared to junction-isolated RESURF LIGBTs or vertical IGBTs. The turn off characteristic shows an extended ‘terrace’ where, after the initial fast transient characteristic of IGBTs due to the loss of the electron current, the current stays almost at the same value for an extended period of time, before suddenly dropping to zero. In this paper, we show that this terrace arises because there is a value of LIGBT current during switch off where the rate of expansion of the depletion region with respect to the anode current is infinite. Once this level of anode current is approached, the depletion region starts to expand very rapidly, and is only stopped when it reaches the n-type buffer layer surrounding the anode. Once this happens, the current rapidly drops to zero. A quasi-static analytic model is derived to explain this behaviour. The analytically modelled turn off characteristic agrees well with that found by numerical simulation.

A study of frequency response in silicon heterojunction bipolar transistors with amorphous silicon emitters

A detailed physical model of amorphous silicon (a-Si:H) is incorporated into a two-dimensional device simulator to examine the frequency response limits of silicon heterojunction bipolar transistors (HBTs) with a-Si:H emitters. The cutoff frequency is severely limited by the transit time in the emitter space charge region, due to the low electron drift mobility in a-Si:H, to 98 MHz which compares poorly with the 37 GHz obtained for a silicon homojunction bipolar transistor with the same device structure. The effects of the amorphous heteroemitter material parameters (doping, electron drift mobility, defect density and interface state density) on frequency response are then examined to find the requirements for an amorphous heteroemitter material such that the HBT has better frequency response than the equivalent homojunction bipolar transistor, We find that an electron drift mobility of at least 100 cm/sup 2/ V/sup -1/ s/sup -1/ is required in the amorphous heteroemitter and at a heteroemitter drift mobility of 350 cm/sup 2/ V/sup -1/ s/sup -1/ and heteroemitter doping of 5/spl times/10/sup 17/ cm/sup -3/, a maximum cutoff frequency of 52 GHz can be expected.

Analytic modelling of the thin-film field-emission triode

Abstract An analytic model for the thin-film field-emission triode has been developed which allows fast and accurate calculation of the electric field distribution on the surface of the thin-film cathode for a wide range of device dimensions and operating voltages. The model can also be used to calculate the potential distribution throughout the device. The model is used together with the Fowler–Nordheim equation and with the published field-emission data on a carbon nanotube film to calculate the profiles of emission current along the surface of the thin-film cathode for a number of geometries. Non-uniform emission is shown to be a problem, which will result in undesirably large gate currents. Increasing the anode voltage to bias the cathode to just below its emission threshold even when the gate is off is shown to be an effective means of providing uniform emission when the gate is turned on while preserving a sufficiently high on/off ratio of emitted current.

3D-RESURF SOI LDMOSFET for RF power amplifiers

There has been an on going effort to improve RF performance in LDMOSFETs for high voltage applications. This paper examines the suitability of a 3D-RESURF LDMOSFET on SOI technology for RF power applications using the 3D-device simulator, Davinci. For the same blocking voltage rating, the 3D-RESURF device has improved current handling capability at high gate voltages. This in turn causes the transconductance to be higher, leading to overall better RF performance.