A. Poppe

Thermal Measurement and Modeling of Multi-Die Packages

Thermal measurement and modeling of multi-die packages with vertical (stacked) and lateral arrangement became a hot topic recently in different fields like RAM chip packaging or LEDs and LED assemblies. In our present study, we present results for a more complex structure: an opto-coupler device with four chips in a combined lateral and vertical arrangement. The paper gives an overview of measurement and modeling techniques and results for stacked and multichip module (MCM) structures. It describes actual measurement results along with our structure function-based methodology which helps validating the detailed model of the package being studied. For stack-die packages, we suggest an extension of the DELPHI model topology. Also, we show how one can derive junction-to-pin thermal resistances with a technique using structure functions.

On the standardization of thermal characterization of LEDs

Nowadays the demand for thermal standards for power LEDs is increasing. On the one hand metrics for fair comparison of competing products are needed; on the other hand, designers of power LED-based applications demand reliable and meaningful data for their daily work. Todays data sheet information does hardly meet any of these requirements. In earlier papers [1] [2] we compared the current situation in the LED world with the situation in the IC world over twenty years ago, observed that much can be learned from the progress achieved, and concluded with a proposal for action. This paper addresses thermal issues that are specific to light emitting diodes (in fact, also semiconductor devices), the drawbacks of the current situation with respect to the information in the data sheets, and emphasizes the need for electro-thermal models. It also includes a new version of the proposal for action. Note: This paper is an update of a paper presented at THERMINIC 2008[3].

Dynamic compact models of cooling mounts for fast board level design

Traditional board level thermal simulators provide temperature distribution on the board only. Recently developed simulators calculate exact junction temperatures obtained by the co-simulation of the detailed board model and the dynamic compact models of the devices the on board. The DELPHI project targeted the generation of steady-state compact models while the aim of the recent PROFIT project was the same for dynamic simulations. This paper tries to extend the DELPHI and PROFIT methodologies to allow completing dynamic compact models of device packages with compact models of cooling assemblies for the same purpose: co-simulation with the detailed board model. A few case studies are presented showing how such models can be constructed using structure functions and transient model fitting tools.

Temperature dependent thermal resistance in power LED assemblies and a way to cope with it

Different high-end white power LEDs from different LED vendors were studied. The aim of the study was to find the optimal choice of LEDs and thermal management solutions for a street-lighting application. The primary concern was the (real) junction-to-heatsink thermal resistance of the LED or LED assembly and the real junction temperature and the actual light output of the individual LEDs under test. Since in many cases the junction-to-heatsink thermal resistance showed temperature dependence, like-with-like comparison in terms of light output characteristics was done as function of the real junction temperature instead of the reference temperature.

A methodology for the generation of dynamic compact models of packages and heat sinks from thermal transient measurements

In this paper we present a methodology that we have recently elaborated for the generation of transient compact models of packages and heat sinks entirely from measured thermal transient results. The main advantage of generating the models from measured results is the time-gain. We do not need to build up the detailed structural model of the package or the heat sink in order to simulate it, as suggested by the DELPHI methodology. An additional advantage is that the lengthy transient simulations are not needed. In the paper we first summarize the way of generating the compact models of packages and heat sinks from measurements. After this we present how to use the obtained dynamic compact package models in board level simulators, that are extended with the feature of calculating with compact models.

A procedure to correct the error in the structure function based thermal measuring methods

In this paper a methodology is presented to correct the systematic error of structure function based thermal material parameter measuring methods. This error stems from the fact that it is practically impossible to avoid parallel heat-flow paths in case of forced one-dimensional heat conduction. With the presented method we show how to subtract the effect of the parallel heat-flow paths from the measured structure function. With this correction methodology the systematic error of structure function based thermal material parameter measuring methods can be practically eliminated. Application examples demonstrate the accuracy increase obtained with the use of the method.

Inclusion of RC compact models of packages into board level thermal simulation tools

The paper presents an algorithm and a methodology for the co-simulation of packages, given with the RC compact models, and the printed circuit boards. This enables correct detailed consideration of the heat transfers in the board, and in addition the calculation of the exact junction temperatures in the packages. The methodology offers the possibility of considering individual heat transfer coefficients for each package, or even to each side of the package, depending on the compact models, and on user requirements. The main advantage is that the methodology keeps the extreme speed and user friendliness of the board level solvers.

Design issues of a multi-functional intelligent thermal test die

Thermal characterization of IC packages and packaging technologies is becoming a key task in thermal engineering. To support this by measurements, we developed a family of thermal test chips that allows a wide range of possible applications. Our chips are based on the same basic cell that is mainly covered by dissipating resistors and also contains a frequency output temperature sensor. These basic cells are organized into arrays of different size. The arrays are designed so that larger arrays can also be built for tiling up larger package cavities. The first member of the family, TMC81, has been manufactured and measurements show that the goals aimed for at the design stage have been achieved.

Issues in junction-to-case thermal characterization of power packages with large surface area

There are several ways to define the junction-to-case thermal resistance; however, it is rather challenging to characterize the heat-flow in a package by a single number in an accurate and reproducible way. For many power package families such as TO-type packages the thermal transient testing and the so-called dual interface method can give reliable results. The diverging point of structure functions from dual thermal transients gives a good picture of the material interfaces in such structures. However, the location and nature of the diverging point strongly depends on the shape and direction of the heat-spreading. If the package area is much larger than the dissipating chip the shape of the heat-flow changes when using different interfaces. This causes structure functions corresponding to the two setups deviate much before reaching the case surface. In this paper the origin of this phenomenon is investigated. Measurement and simulation results are compared on different large IGBT modules with several modifications in their structure enabling a detailed analysis of the heat-flow path. A comparison is given between heating only a small fraction of a large module and heating all chips. Some samples went through thermal cycling reliability tests which resulted in cracks below the chips. The effect of the reduced die-attach area is visualized with the help of structure functions.

New way for thermal transient testing [IC packaging]

This paper introduces a new concept of thermal transient measurement of IC packages without a tester. The thermal transient test kit described here consists of a test chip, dedicated software running on a PC and a special cable connecting the PC to the IC package which encapsulates the test chip. The functionality of the thermal transient test equipment is realized by the test chip itself and the measurement software. The software performs both the control of the measurement and the results evaluation. The final output of the evaluation software is a compact model network and the structure function, describing the properties of the heat conduction path realised by the IC package under test. The use of the test kit and the capabilities of its evaluation software are demonstrated by a few examples.