Gabor Farkas

Thermal investigation of high power Optical Devices by transient testing

In case of opto-electronic devices, the power applied on the device leaves in a parallel heat and light transport, the interpretation of R/sub th/ is not obvious. The paper shows results of a combined optical and thermal measurement for the characterization of power light emitting diodes (LEDs). A model explaining R/sub th/ changes at different current levels is proposed.

Thermal Measurement and Modeling of Multi-Die Packages

Thermal measurement and modeling of multi-die packages with vertical (stacked) and lateral arrangement became a hot topic recently in different fields like RAM chip packaging or LEDs and LED assemblies. In our present study, we present results for a more complex structure: an opto-coupler device with four chips in a combined lateral and vertical arrangement. The paper gives an overview of measurement and modeling techniques and results for stacked and multichip module (MCM) structures. It describes actual measurement results along with our structure function-based methodology which helps validating the detailed model of the package being studied. For stack-die packages, we suggest an extension of the DELPHI model topology. Also, we show how one can derive junction-to-pin thermal resistances with a technique using structure functions.

Thermal transient characterization methodology for single-chip and stacked structures

High-power semiconductor packages typically exhibit a 3D heat flow, resulting in large lateral changes in chip and case surface temperature. For single-chip devices we propose to use an unambiguous definition for the junction-to-case thermal resistance as a key parameter, based on a transient measurement technique with much higher repeatability, also for very low thermal resistances compared to a two-point thermal resistance measurement. The technique is illustrated on thermal transient measurements of power MOSFETs. A comparison between different thermal coupling to the ambient is used to demonstrate the methods capability to reveal even subtle internal details of the package. The concept is extended to multichip and stacked-chip structures, where transfer impedances have to be introduced. Here, the dynamic properties of the package are important and complex impedance mapping is the proper way to characterize the package.

Multi-domain simulation and measurement of power LED-s and power LED assemblies

Besides their electrical properties the optical parameters of LEDs also depend on junction temperature. For this reason thermal characterization and thermal management plays important role in case of power LEDs, necessitating tools both for physical measurements and simulation. The focus of this paper is a combined electrical, thermal and optical characterization of such devices. In terms of simulation a novel approach of board-level electro-thermal simulation is presented whereas in terms of measurement, a combined thermal and radiometric characterization method is discussed

Short time die attach characterization of leds for in-line testing application

The qualification of the die attach of light emitting diodes (LED) is a very important element of predicting the reliability of the package, as the temperature of the chip is strongly affected by the quality of the die attach. LED manufacturers are seeking for solutions to be able to test die attach quality in mass production. This paper describes our findings regarding LED package testing with a focus on die attach quality testing, necessary short measurement times only. Requirements against the physical testing and the further processing are shown based on our experimental findings.

Boundary condition independent dynamic compact models of packages and heat sinks from thermal transient measurements

In this paper a methodology developed for the generation of transient compact models of packages and heat sinks from measured thermal transient results is described. The main advantage of generating dynamic compact models solely from measured results is the time-gain: the lengthy transient simulations, suggested by the DELPHI methodology can be omitted. After summarizing the procedure of generating the compact models of packages and heat sinks from measurements the use of the obtained dynamic compact package models in board level simulators, extended with the feature of calculating with compact models is presented.

Emerging standard for thermal testing of power LEDs and its possible implementation

Nowadays the demand for thermal standards for power LEDs is increasing. On one hand metrics for fair comparison of competing products are needed; on the other hand, designers of power LED-based applications need reliable and meaningful data for their daily work. Todays data sheet information does hardly meet any of these requirements. In 2008 the JEDEC JC15 committee on thermal standardization of semiconductor devices decided to take action and created a task group to deal with thermal standardization issues of power LEDs. CIE has also created two new technical committees (TC2-63, TC2-64) which also aim to address thermal issues during measurement of high brightness / high power LEDs. This paper deals with thermal issues that are specific to light emitting diodes by describing novel test methods which may form basis of new measurement guidelines or standards including combined thermal and radiometric measurement of LEDs. Thermal issues in connection with short pulse measurements of LEDs and some thermal aspects of LM80 tests are also discussed.

Package Characterization: Simulations or Measurements?

As the functionality of thermal simulators gets more and more complex, measurement techniques also improve. Thermal engineers face and increasingly difficult task to make the right selection from the existing tools. In this paper the applicability of the JEDEC JESD 51-1 static measurement method is compared to mainstream simulation tools especially MCAD or EDA embedded CFD solutions. Both techniques are opposed to each other in terms of required time and other expense factors. In this paper we discuss when different aspects of trade-offs to be made between thermal simulation and physical testing.

Design issues of a multi-functional intelligent thermal test die

Thermal characterization of IC packages and packaging technologies is becoming a key task in thermal engineering. To support this by measurements, we developed a family of thermal test chips that allows a wide range of possible applications. Our chips are based on the same basic cell that is mainly covered by dissipating resistors and also contains a frequency output temperature sensor. These basic cells are organized into arrays of different size. The arrays are designed so that larger arrays can also be built for tiling up larger package cavities. The first member of the family, TMC81, has been manufactured and measurements show that the goals aimed for at the design stage have been achieved.

Issues in junction-to-case thermal characterization of power packages with large surface area

There are several ways to define the junction-to-case thermal resistance; however, it is rather challenging to characterize the heat-flow in a package by a single number in an accurate and reproducible way. For many power package families such as TO-type packages the thermal transient testing and the so-called dual interface method can give reliable results. The diverging point of structure functions from dual thermal transients gives a good picture of the material interfaces in such structures. However, the location and nature of the diverging point strongly depends on the shape and direction of the heat-spreading. If the package area is much larger than the dissipating chip the shape of the heat-flow changes when using different interfaces. This causes structure functions corresponding to the two setups deviate much before reaching the case surface. In this paper the origin of this phenomenon is investigated. Measurement and simulation results are compared on different large IGBT modules with several modifications in their structure enabling a detailed analysis of the heat-flow path. A comparison is given between heating only a small fraction of a large module and heating all chips. Some samples went through thermal cycling reliability tests which resulted in cracks below the chips. The effect of the reduced die-attach area is visualized with the help of structure functions.