A. Stojcevski

Project Based Learning Curriculum in Microelectronics Engineering

In this paper, the student-centered pedagogical program used in the School of Electrical Engineering with a case study illustrating and describing the project-based curriculum in microelectronics is described. A case study project also described in the paper shows that the project-based learning method engages students in a deeper learning where not only emphasis is given to the final product, but also the process to get there.

High Speed Ultra Wide Band Comparator in Deep Sub-Micron CMOS

This paper presents the implementation of a high speed low power over sampled CMOS comparator for use in a reconfigurable flash analog to digital converter (ADC) as part of a direct sequence - spread spectrum (DS-SS) based ultra wide band (UWB) radio receiver. The comparator was designed using a 90 nanometre (nm) CMOS technology process. The switching speed of the comparator is 4 giga-samples per second (GSps) for a 528 megahertz (MHz) input bandwidth. The comparator operates on a 1 V power supply. The total input referred offset of the comparator at 4 GSps is 33.1 mV which is about 0.6 LSB for a 4 bit flash converter.

Implementation of magnitude estimation algorithm for hearing aid

The hardware implementation of a magnitude estimation algorithm for a hearing aid is presented in this paper. Digital signal processing (DSP) is used in almost all the modern digital hearing aids available today. The processing of the sound signals is carried out in the frequency domain. Fast Fourier transform (FFT) converts the time domain signal to frequency domain and gives a complex number output representing each frequency component in the audible frequency spectrum. The magnitude estimation block estimates the magnitude of these complex numbers. This estimated magnitude is used as an input to apply various DSP algorithms for sound processing in the hearing aid. In this paper the Alpha max-Beta min and the coordinate rotation digital computer (CORDIC) algorithms for magnitude estimation of a complex number are compared from the hardware implementation point of view. The emphasis of this paper is the hardware implementation of the CORDIC algorithm in application specific integrated circuit (ASIC) design flow and its performance analysis. The CORDIC algorithm is implemented because of its accuracy and implementation simplicity. The paper also presents the simulation and synthesis results obtained for hardware implementation of four iterations of the CORDIC algorithm for magnitude estimation.

A reconfigurable analog-to-digital converter for UTRA-TDD mobile terminal receiver

A reconfigurable analog-to-digital converter (ADC) has been proposed for a mobile terminal. This architecture scales the digital word length (bits) by automatically monitoring desired power and adjacent channel interference power. This leads to power consumption savings, depending on the number of bits used. The architecture can scale between a minimum of 4 bits and maximum of 16 bits. The new reconfigurable ADC was applied to Time-Division-Duplex (TDD) mode of UMTS Terrestrial Radio Access (UTRA) system and results show that this reconfigurable ADC can save up 75 % of the power consumption when compared with the power consumption of a standard 16-bit analog-to-digital converter.

A high speed analog to digital converter for ultra wide band applications

Over the past few years Ultra Wide Band (UWB) technology has taken the realms of communications circuit design to new levels. This paper demonstrates the design and simulation of a very high speed Flash Analog to Digital Converter (ADC) for UWB applications. The ADC was implemented in 90 nanometre (nm) CMOS design process. The converter works at an optimal sampling rate of 4.1 Gig-Samples per second (Gsps) for an 800 MHz input bandwidth corresponding to a 1V full scale reference. The converter has moderate linearity error tolerance of about ±1 LSB (62.5 mV) without use of any averaging techniques. The ADC works on a 1V supply and has an overall power consumption of 114 mW.

MEMS-based inductor implementation for RF front end of mobile terminal

There has been significant growth in the wireless market where new applications are accompanied with strict design goals such as low cost, low power dissipation and small form factor. Large capacity and range for new applications are the driving force for development of new standard such as third generation mobile system (3G). Recent research results show that the development that was not possible with current IC technology is made possible with MicroElectroMechanical Systems (MEMS) technology. Significant amount of research is taking place to replace the off-chip components with on-chip components to design a high performance receiver front end. The passive components such as switches, capacitors and inductors are integral part of RF front end. High quality (Q) inductors are used to design RF front-end components such as voltage-controlled oscillator (VCO) and low noise amplifier (LNA). However, they are the bottleneck in achieving the on-chip optimum components, because of Q factor dependence on parasitic effects, limiting the performance. In recent research publications different on-chip inductor structures such as coil, polygon, rectangular and stacked configurations have been suggested and used to implement high value of inductance. In this paper design and implementation issues of MEMS inductor are presented. The paper is divided in two sections, the first section presents the role of MEMS based passive components and second section presents design issues, implementation and analysis of different MEMS based inductors.

A tunable VCO for multistandard mobile receiver

This paper presents a tunable CMOS voltage controlled oscillator (VCO) used to generate 1.8 GHz, 3.6 GHz and 4.2 GHz frequencies for multistandard mobile receiver. The switch architecture is used to combine three VCOs to get a better phase noise performance tunable VCO. The architecture is able to select the operating frequency based on a control signal. The VCOs are independently designed with the view of switch architecture combination, so the phase noise performance of this architecture is well below the specification of GSM and WCDMA standards.

A 0.8 GHz to 1 GHz 0.25 μm CMOS low noise amplifier for multi-standard receiver

A single-ended low noise amplifier (LNA) for a multi-standard (800 to 1000 MHz) mobile receiver that covers GSM and 3G respectively, has been designed and simulated in a 0.25 mum CMOS technology process. This LNA makes part of a larger system to cover GSM and 3G bands from 800 to 2100 MHz but this work only focuses on lower bands. The circuit topology is based on inductively degenerated common source (IDCS). Circuit simulations indicate a power gain of 12 dB, a noise figure of 0.7 dB with IIP3 and 1-dB compression point of 0.87 dBm and -2.7 dBm respectively. The current consumption for this circuit is 8.3 mA with voltage supply of 2.5 V.

A 1.8 GHz to 2.1 GHz 0.25 μm CMOS wideband LNA for a multi-standard mobile receiver

A single-ended wideband low noise amplifier for a multi-standard (1.8 GHz to 2.1 GHz) mobile receiver has been designed and simulated in a 0.25 μm CMOS technology process. The circuit topology is based on inductively degenerated common source (IDCS). The enhancement for bandwidth was performed using inductive shunt-peaking that added more freedom to the circuit. Circuit simulation results shows a power gain of 23 dB, a noise figure of 0.6 dB with IIP3 and 1-dB compression point of -5.1 dBm and -17.3 dBm respectively. The current consumption for this circuit is 9.5 mA with voltage supply of 2.5 V.

CMOS ADC with reconfigurable properties for a cellular handset

A low power reconfigurable ADC architecture is described for a mobile terminal receiver. The architecture can automatically scale the resolution by monitoring in-band and out-of-band powers. The architecture performance was evaluated in a simulation UTRA-TDD environment. A power consumption analysis of the implemented architecture is also presented. The UTRA-TDD downlink mode was examined statistically and results show that the reconfigurable architecture can save an average of 74 percent power dissipation for TDD mode when compared to a fixed ADC word length of 16 bits. This will prolong talk and standby time in a mobile terminal.