Jugdutt Singh

Cyclic shifting and time inversion of partial transmit sequences to reduce the peak-to-average power ratio in OFDM

An adaptation of the work by Huber and Muller (see Electronic Letters, vol.33, no.5, p.368-69, 1997) on partial transmit sequences (PTS) for the reduction of the peak-to-average power ratio (PAPR) in orthogonal frequency division multiplexing (OFDM) is described.

FPGA implementation of an OFDM-WLAN synchronizer

In this paper, we present a timing and frequency synchronization scheme and its FPGA implementation for IEEE 802.11a WLAN systems. In the scheme, an efficient double auto-correlation method based on short training symbols is used for timing synchronization. The performance of the proposed method is comparable or even superior to that of the conventional timing synchronization method under multipath fading channels. By averaging the correlation over four short training symbols, the accuracy of frequency synchronization using short training symbols can be improved to a level that the fine frequency synchronization process using long training symbols in the conventional scheme would not be needed. Thus both timing and frequency synchronization can be achieved using short training symbols alone to reduce computational complexity and overhead. Furthermore, the hardware architecture of the proposed synchronization scheme is developed. The synchronizer is mainly made up of correlator, angle calculator and peak detector, which are implemented by an iterative process, a CORDIC circuit and a finite state machine, respectively. Such an architecture results in low implementation complexity and low computational latency.

Xilinx Virtex II Pro implementation of a reconfigurable UMTS digital channel filter

A reconfigurable digital root raised cosine (RRC) filter for a UMTS terrestrial radio access (UTRA) mobile terminal receiver is implemented on a Xilinx Vitrex II Pro Field Programmable Gate Array (FPGA). The filter employs a finite impulse response (FIR) and monitors in-band and out-of-band received signal powers and calculates the appropriate filter length that meets the bit-energy to interference ratio (Eb/No) of the system. The results presented are for the time division duplex (TDD) mode of UTRA.

A 12-bit high performance low cost pipeline ADC

This paper presents the design and implementation of a 2.5V 12-bit high performance and low cost pipeline Analog-to-Digital converter (ADC) architecture using CMOS technology. A modified flash ADC was employed instead of the traditional flash ADC to implement the sub-ADC in the designed pipeline ADC scheme to reduce the device complexity and attain lower system power consumption. The designed pipeline ADC architecture is operated at 400 MHz, consumes a total power of 47.7mW. Results indicates that 40% power saving is obtained at 400MHz when the modified flash ADC is used to implement the pipeline sub-ADC instead of a full flash ADC. Such pipeline ADC is the best candidate for many applications where power and size are the major factors.

A proposed reconfigurable digital filter for a mobile station receiver

A novel reconfigurable digital filter has been proposed for a mobile terminal receiver that can drastically reduce power dissipation dependant on adjacent channel interference. It automatically scales the number of filter coefficients by monitoring the in-band and out-of-band powers. This new filter performance was evaluated in a simulation UTRA-TDD environment because of the large near far problem caused by adjacent channel interference from adjacent mobiles and base stations. The UTRA-TDD downlink mode was examined statistically and results show that this reconfigurable filter can save an average of 75% power dissipation when compared to a fixed filter length of 41. This will prolong talk and standby time in a mobile terminal. The average number of taps was calculated to be 10.1 for an outage of 97%.

Recent Subthreshold Design Techniques

Considering the variety of studies that have been reported in low-power designing era, the subthreshold design trend in Very Large Scale Integrated (VLSI) circuits has experienced a significant development in recent years. Growing need for the lowest power consumption has been the primary motivation for increase in research in this area although other goals, such as lowest energy delay production, have also been achieved through sub-threshold design. There are, however, few extensive studies that provide a comprehensive design insight to catch up with the rapid pace and large-scale implementations of sub-threshold digital design methodology. This paper presents a complete review of recent studies in this field and explores all aspects of sub-threshold design methodology. Moreover, near-threshold design and low-power pipelining are also considered to provide a general review of sub-threshold applications. At the end, a discussion about future directions in ultralow-power design is also included.

Implementation of magnitude estimation algorithm for hearing aid

The hardware implementation of a magnitude estimation algorithm for a hearing aid is presented in this paper. Digital signal processing (DSP) is used in almost all the modern digital hearing aids available today. The processing of the sound signals is carried out in the frequency domain. Fast Fourier transform (FFT) converts the time domain signal to frequency domain and gives a complex number output representing each frequency component in the audible frequency spectrum. The magnitude estimation block estimates the magnitude of these complex numbers. This estimated magnitude is used as an input to apply various DSP algorithms for sound processing in the hearing aid. In this paper the Alpha max-Beta min and the coordinate rotation digital computer (CORDIC) algorithms for magnitude estimation of a complex number are compared from the hardware implementation point of view. The emphasis of this paper is the hardware implementation of the CORDIC algorithm in application specific integrated circuit (ASIC) design flow and its performance analysis. The CORDIC algorithm is implemented because of its accuracy and implementation simplicity. The paper also presents the simulation and synthesis results obtained for hardware implementation of four iterations of the CORDIC algorithm for magnitude estimation.

DSP and ASIC implementation of a channel filter for a 3G UTRA-TDD system

This paper describes the design, simulation and implementation of a high performance low power pulse-shaping FIR filter. The filter is for an UTRA-TDD transmitter. The pulse-shaping filter was implemented on a DSP and as an ASIC. A performance analysis and comparison using industry standard EDA tools was performed. A proposed reconfigurable pulse-shaping filter architecture for the receiver in the mobile terminal is also presented. This novel architecture can drastically reduce power dissipation dependant on adjacent channel interference. It automatically scales the number of filter coefficients by monitoring the in-band and out-of-band powers. This new filter performance was evaluated in a simulation UTRA-TDD environment because of the large near far problem caused by adjacent channel interference from adjacent mobiles and base stations.

High speed analog-to-digital converter for software radio applications

This paper describes the design and performance of a mixed signal, very high speed, analog-to-digital converter implemented using gallium arsenide MESFET technology for software radio applications. The design is module oriented, thus enabling easy cascading into a multi-bit chip. The four-bit circuit dissipates 185.6 miliwatts of power and has a conversion time of 0.75 nsec. The results validate the design technology and techniques used for mixed analog-digital circuit design on a single chip.

Design And Analysis Of Low Power Low Phase Noise VCO

In this paper, a novel methodology to implement a LC tank voltage controlled oscillator (VCO) with lower phase noise is proposed and verified. A relationship between the phase noise, power consumption and the bias current is fully analysed to improve the performance of the VCO. The architecture of the VCO employs two current mirrors one at the top of the cross-coupled complementary VCO and the other at the tail end to balance the impedance and give the exact replica of the current in both the arms of current mirror circuit. The phase noise measured is -110.9 dBc/Hz at the offset frequency of 100KHz, -126.4 dBc/Hz at 600kHz and -140.5 dBc/Hz at 3MHz from the carrier frequency. The VCO consumes only 1.72mW of power at 2V supply. Results show that a 33% reduction in power consumption is achieved as compared to the VCO using a tail current mirror and 46.75% to the VCO without current mirrors