Hai Phuong Le

A 12-bit high performance low cost pipeline ADC

This paper presents the design and implementation of a 2.5V 12-bit high performance and low cost pipeline Analog-to-Digital converter (ADC) architecture using CMOS technology. A modified flash ADC was employed instead of the traditional flash ADC to implement the sub-ADC in the designed pipeline ADC scheme to reduce the device complexity and attain lower system power consumption. The designed pipeline ADC architecture is operated at 400 MHz, consumes a total power of 47.7mW. Results indicates that 40% power saving is obtained at 400MHz when the modified flash ADC is used to implement the pipeline sub-ADC instead of a full flash ADC. Such pipeline ADC is the best candidate for many applications where power and size are the major factors.

Design And Analysis Of Low Power Low Phase Noise VCO

In this paper, a novel methodology to implement a LC tank voltage controlled oscillator (VCO) with lower phase noise is proposed and verified. A relationship between the phase noise, power consumption and the bias current is fully analysed to improve the performance of the VCO. The architecture of the VCO employs two current mirrors one at the top of the cross-coupled complementary VCO and the other at the tail end to balance the impedance and give the exact replica of the current in both the arms of current mirror circuit. The phase noise measured is -110.9 dBc/Hz at the offset frequency of 100KHz, -126.4 dBc/Hz at 600kHz and -140.5 dBc/Hz at 3MHz from the carrier frequency. The VCO consumes only 1.72mW of power at 2V supply. Results show that a 33% reduction in power consumption is achieved as compared to the VCO using a tail current mirror and 46.75% to the VCO without current mirrors

A fully-on-chip wideband low noise amplifier for radio telescope applications

This paper presents the design and implementation of a fully on-chip wideband LNA using 0.25-micron Silicon-on-Sapphire (SOS) technology for the next-generation radio telescope application, the Square Kilometre Array (SKA), which demands ultra low noise and wideband operation. The proposed LNA design employs a cascaded inductive degeneration architecture with intermediate LC architecture, resulting in a broadband input matching. The LNA is optimised for minimum noise figure (NF) by employing an external gate-source capacitor which is perfectly matched with a high quality factor (Q) inductors. After optimisation, the LNA achieved a NF from 0.56dB to 0.67dB over 1.1GHZ-band with a minimum gain of 14.9dB at a 2.5-V power supply.

A very high Q-factor inductor using MEMS technology

This paper presents the design and optimisation of a very high Quality (Q) factor inductor using MEMS technology for 10GHz to 20GHz frequency band. The effects of various parameters of a symmetric inductor structure on the Q-factor and inductance are thoroughly analysed. The inductor has been designed on Silicon-on-Sapphire (SOS) substrate because it offers superior characteristics of low substrate loss due to the high resistivity of the sapphire material and low capacitive coupling to the substrate. It is also been suspended from the substrate in order to reduce the substrate loss and improved the Q factor. Results indicate that a maximum Q factor of 192 for a 1.13nH inductance at 12GHz is achieved after optimising the symmetric inductor.

Potential of Reconfigurable Digital Backend in UWB Receiver for Wireless Sensor Network

Wireless sensor networks (WSNs) open a new paradigm for extracting data from the environment and enable reliable monitoring/controlling for a large number of applications areas. They demand ultra low power consumption from the design components as they are battery operated. Various power reduction techniques and algorithms for the data acquisition block in WSN system are proposed in the literature. This paper presents the application of ultra wideband (UWB) communication technology for the transceiver block in a WSN. The present digital UWB radio architecture uses significant parallelism in the digital backend during synchronisation operation which increases power consumption of the entire system. This paper investigates the actual parallelism required for different channel impulses and time delays. This is done in order to estimate the potential for power saving that can be achieved by incorporating real time re configurability in digital backend of the UWB receiver. It is observed that reconfiguration has a potential of achieving an average relative power saving of 47%, for a typical operating condition. This is verified by power consumption results obtained for the FPGA implementation of pulse matched filter in the digital backend of a UWB receiver.

Investigation of Reconfigurability for the Digital Backend of Ultra Wideband Receiver

The next generation Wireless Personal Area Network and Wireless Sensor Network applications demand portability and ultra low power operation. Ultra Wideband communication has the potential to achieve these requirements due to possibility of digital implementation. The mostly digital UWB radio is designed to cope up with worst case channel condition and uses heavy parallelism in the digital backend leading to high power consumption during acquisition and synchronisation mode. However, for UWB pulse propagation, the wireless channel and time delay may vary due to various factors. This paper analyses the effect of different channel impulses and time delays on the required parallel hardware for receiver processing. This analysis is performed in order to investigate the real time reconfigurability approach for the digital UWB receiver in order to save power. The analysis shows that introduction of reconfigurability has a potential to reduce power consumption.

A 2mA-2.5V low phase noise multi-standard VCO

This paper presents the design of a voltage controlled oscillator (VCO) for multi-standard wireless receiver covering Global Standards for Mobile (GSM), Digital Communication Systems (DCS), Personal Communication Systems (PCS), and Universal Mobile Telecommunication System (UMTS) standards. An effective frequency planning scheme that requires the VCO to tune from 3.2GHz to 4.1GHz and generate multiple bands using frequency division is presented. The presented VCO design employs two current mirrors for efficient current control, a specially designed inductor with quality factor (Q) of 111, and multiple noise filtering techniques to reduce flicker noise components. The proposed multi-standard VCO is designed using 0.25µm silicon-on-sapphire (SOS) technology and consumes only 5.18mW power at 4.1GHz operating frequency. The VCO achieves phase noise of −132dBc/Hz and −141dBc/Hz at 1MHz and 3 MHz offsets respectively resulting in figure of merit (FOM) of −197dBc/Hz/mW.

Towards Real Time Parallelism Reduction for Digital UWB Receiver

The mostly digital ultra wideband (UWB) receiver, designed for worst case channel conditions, uses significant parallelism in the digital backend which increases power consumption. However, the wireless channel may vary due to factors such as time delay and channel impulse response. This paper investigates and analyses effects of these factors on receiver parallelism for determining sufficient hardware required for different channel conditions. This analysis is performed for exploring real time parallelism reduction to save power in the digital backend of the UWB receiver. The paper also discusses the functional blocks and design constraints of one of the parallelism reduction algorithm.

A semi-custom ASIC implementation of an intelligent control algorithm for a reconfigurable data acquisition system

This paper presents the application specific integrated circuit (ASIC) implementation of an intelligent controller for a reconfigurable data acquisition (DAQ) system. The DAQ system is employed in a digital relay for power system protection application. The controller is the intelligence behind the reconfigurable architecture. It continuously monitors the voltages and currents to detect the appearance of an abnormal condition on the power transmission network. Then it will send signals to adjust DAQ system sampling speed and filter cut-off frequency for properly detecting the fault location and properly analysing the fault. A novel approach to determine the line impedance angle has been proposed. This approach eliminates the square-root and arc-tan operations to reduce the cost of the semi-custom ASIC implementation of the intelligent controller. Analysis revealed that the intelligent controller achieved a maximum operating frequency of 100MHz, with 10ns critical path delay. The controller core utilises an area of 1.9mm2.

Very High Q, NEMS Inductor for 12GHz Wireless Sensor Applications

This paper presents the design and optimisation of high quality (Q) factor inductors using Micro/Nano Electro-Mechanical Systems (NEMS/MEMS) technology for 10GHz to 20GHz frequency band. Three inductors have been designed with rectangular, circular and symmetric topologies. Comparison has been made amongst the three to determine the best Q-factor. Inductors are designed on Silicon-on-Sapphire (SOS) because of its advantages including high resistivity and low parasitic capacitance. The effects of various parameters such as outer diameter (OD), the width of metal traces (W), the thickness of the metal (T) and the air gap (AG) on the Q-factor and inductance performances are thoroughly investigated. Results indicate that the symmetric inductor has highest Q-factor with peak Q of 192 at 12GHz for a 1.13nH.