A. Subirats

Impact of Single Charge Trapping on the Variability of Ultrascaled Planar and Trigate FDSOI MOSFETs: Experiment Versus Simulation

The impact of single charge trapping on the threshold voltage Vt of ultrascaled fully depleted silicon-on-insulator transistors is investigated through dynamic variability measurements and 3-D electrostatic simulations. In these undoped Si channel devices, Vt shifts induced by individual trapping events are exponentially distributed with distribution tail similarly as in BULK devices. This typical dependence is explained by the high sensitivity of Vt -with a bell-like shape-on the position of the trap over the channel. The tail, on the other hand, is attributed to defects in the buried oxide. Finally, device scaling is showed to increase dynamic Vt variability. In particular, the impact of a single charge on Vt is found to scale with the inverse of the device area.

Efficient physical defect model applied to PBTI in high-κ stacks

Instabilities in MOS-based devices with various substrates ranging from Si, SiGe, IIIV to 2D channel materials, can be explained by defect levels in the dielectrics and non-radiative multi-phonon (NMP) barriers. However, recent results obtained on single defects have demonstrated that they can show a highly complex behaviour since they can transform between various states. As a consequence, detailed physical models are complicated and computationally expensive. As will be shown here, as long as only lifetime predictions for an ensemble of defects is needed, considerable simplifications are possible. We present and validate an oxide defect model that captures the essence of full physical models while reducing the complexity substantially. We apply this model to investigate the improvement in positive bias temperature instabilities due to a reliability anneal. Furthermore, we corroborate the simulated defect bands with prior defect-centric studies and perform lifetime projections.

MOVPE In1−xGaxAs high mobility channel for 3-D NAND memory

Epitaxially grown In_1-xGa_xAs is integrated for the first time as replacement of polycrystalline silicon (Si) channel down to 45 nm diameter for 3-D NAND memory application. Channels with different compositions are obtained after careful surface preparation by tuning growth conditions such as: temperature, choice of precursors and flow ratio. In_1-xGa_xAs shows superior conduction properties than poly-Si channel: higher I_on and transconductance (g_m). Potentially good memory operations are also found.

Comparative experimental analysis of time-dependent variability using a transistor test array

As the minimum transistor length reaches the deca-nanometer scale, both time-zero and time-dependent variability, the latter including Random Telegraph Noise (RTN) and Bias Temperature Instability (BTI), become a great concern for IC design. Accurate statistical models describing these two variability sources are therefore necessary in order to design reliable circuits and systems. This paper gives insights in the geometric scaling of these variabilities and analyzes time-dependent variability through three different measurement techniques: 2-point Measure-Stress-Measure, Time-Dependent Defect Spectroscopy, and fine-step Id-Vg. Advantages and downsides of each technique are discussed and compared.

Impact of backside interface on Hot Carriers degradation of thin film FDSOI Nmosfets

Based on simulation results, we show that defects at the Si/Box interface of FDSOI transistors can have a detrimental impact on reliability. In particular, attention is paid to Hot Carriers degradations (HC) on ultra thin film FDSOI NMOSFETs for which defects can be created very close to the back gate interface. A new technique based on capacitance measurements is proposed to localize HC degradation at front gate and/or back gate interface on FDSOI transistors. Thanks to this method, it is shown that, similarly to bulk technologies, only the front gate interface is degraded during a classical HC stress. Finally, despite the presence of an additional Si/BOx interface, FDSOI NMOSFETs down to 30nm gate length exhibit HC lifetimes over 10 years, even when a back bias is applied.

Impact of discrete trapping in high pressure deuterium annealed and doped poly-Si channel 3D NAND macaroni

In this paper, the influence of different processes on electron trapping in vertical 3D NAND macaroni has been investigated. Through slow Id-Vg measurements and RTN analysis, it is shown that doping can cure poly-Si channel defects while deuterium (D2) anneal can passivate both traps present in the channel and in the ONO gate stack. Finally, it is shown that the D2 anneal can also help to improve the retention after cycling.

In Depth Analysis of Post-Program VT Instability after Electrical Stress in 3D SONOS Memories

Through Post-Program-Discharge measurements we achieve in-depth understanding of the ONO stack degradation observed in 3D SONOS memories that results in VT instabilities after the program pulse. We demonstrate that hole injection during erase is degrading the Tunnel Oxide, leading to formation of defects, that can be charged during program but emit electrons soon after. Through device simulations, we could also achieve a precise profiling in space and energy of these stress-generated SiO2 defects and develop a complete model of charge loss in degraded devices.

Gate stack thermal stability and PBTI reliability challenges for 3D sequential integration: Demonstration of a suitable gate stack for top and bottom tier nMOS

3D Sequential integration has been envisioned to stack transistors in the same front-end process. A crucial challenge is the management of the thermal budget. This work focuses on Si nMOS gate stack challenges, specifically: for a top tier device, by inserting a thin LaSiOx interlayer between SiO2 and HfO2 a sufficient PBTI reliability is demonstrated without resorting to unsuitable high temperature anneals. This gate stack also offers good thermal stability for a pMOS over nMOS scenario.

Feasibility of In x Ga 1– x As High Mobility Channel for 3-D NAND Memory

Epitaxial In_xGa_1-xAs is grown by metal organic vapor phase epitaxy as replacement of polycrystalline silicon (Si) channel for high-density 3-D NAND memory applications. The most challenging steps to integrate In_xGa_1-xAs are thoroughly discussed; their impact on the electrical performances are investigated and the tunnel oxide (TuOx) quality is assessed. In_xGa_1-xAs channels with a diameter down to ~45 nm and different In concentrations are obtained after using two alternative surface preparation routes: HCl and Cl₂. Thanks to the lower thermal budget involved, Cl₂ seems the most suitable route to preserve the thickness of the TuOx. In_xGa_1-xAs channels with In concentration, x, higher than 0.45 have superior conduction properties compared with poly-Si channel, showing higher ION and transconductance.

Comphy — A compact-physics framework for unified modeling of BTI

Abstract Metal-oxide-semiconductor (MOS) devices are affected by generation, transformation, and charging of oxide and interface defects. Despite 50 years of research, the defect structures and the generation mechanisms are not fully understood. Most light has been shed onto the charging mechanisms of pre-existing oxide defects by using the non-radiative multi-phonon theory. In this work we present how the gist of physical models for pre-existing oxide defects can be efficiently abstracted at a minimal loss of physical foundation and accuracy. Together with a semi-empirical model for the generation and transformation of defects we establish a reaction-limited framework for unified simulation of bias temperature instabilities (BTI). The applications of the framework we present here cover simulation of BTI for negative (NBTI) and positive (PBTI) gate voltages, life time extrapolation, AC stress with arbitrary signals and duty cycles, and gate stack engineering.