A. Arreghini

Highly Scaled Vertical Cylindrical SONOS Cell With Bilayer Polysilicon Channel for 3-D nand Flash Memory

A vertical cylindrical SONOS cell with a novel bilayer polysilicon channel down to 22-nm diameter for 3-D NAND Flash memory is successfully developed. We introduce a thin amorphous silicon layer along with the oxide-nitride-oxide (ONO) gate stack inside the memory hole. This silicon layer protects the tunnel oxide during opening of the gate stack at the bottom of the memory hole, after which it serves as the first layer of the bilayer polysilicon channel. This approach enables the 3-D architecture to achieve minimum cell area (4F2, with F being the feature size) without the need for the so-called pipeline connections. The smallest functional cells have the memory hole diameter F = 45 nm, resulting in 22-nm channel diameter. In case 16 cells are stacked, F = 45 nm would correspond to an equivalent 11-nm planar cell technology node. Excellent program/erase and retention obtained with the all-deposited ONO stack are demonstrated.

Validation of Retention Modeling as a Trap-Profiling Technique for SiN-Based Charge-Trapping Memories

We applied the developed trap spectroscopy by charge injection and sensing to validate the extraction of the silicon nitride trap distribution (both in space and energy) from the modeling of retention transients of charge-trapping memories. We compared three different types of silicon nitrides using these two techniques, and similar distributions were extracted, thus confirming the validity of the charge profiles resulting from the modeling of retention transients and the physics of the proposed model, based on two main mechanisms of charge loss: Poole-Frenkel emission (dominating at high temperature) and direct tunneling (dominating at room temperature).

A Comprehensive Understanding of the Erase of TANOS Memories Through Charge Separation Experiments and Simulations

We investigate and quantify the role played by electrons and holes during the erase operation of TANOS memories by means of charge separation experiments and physics-based simulations. Results demonstrate that electron emission via trap-to-band tunneling dominates the first part of the erase operation, whereas hole injection prevails in the remaining part of the transient. In addition, we show that the efficiency of the erase operation is high and constant mainly because of the high energy offset between nitride and alumina valence bands. Our results clearly identify the physical mechanisms responsible for TANOS erase and allow deriving some important guidelines for the optimization of this operation.

Electron Trap Profiling Near

The goal of this letter is to investigate and characterize the defects at the Al2O3/gate interface in TANOS memory stacks. To this purpose, gate-side trap spectroscopy by charge injection and sensing is applied on devices featuring different metal gates and different postdeposition anneals. The results show that a high concentration of defect is present in crystalline samples with a TaN or TiN gate.

\hbox{Al}_{2} \hbox{O}_{3}

For future high density storage memories, 3D vertical poly-Si channel SONOS devices are emerging as the most prominent alternative because of the extreme reduction of cost per bit (1-3). This architecture, however, faces critical reliability issues related to the highly defective channel (4-5). For instance, we recently showed that discrete current drops and fluctuations (RTN) are clearly observed in the transfer characteristics (ID vs. VG) of these nanoscale vertical nFETs (Fig. 1). These instabilities were linked to single electron trapping/detrapping processes (6-7), which potentially may cause read errors during operation (4-5). The present paper therefore aims at characterizing these adverse switching traps to gain insight into their physical properties. A statistical comparison among different polysilicon channels is presented and benchmarked against monocrystalline planar nFETs. We reveal that a significant part of the switching traps reside in the poly-Si channel.

/Gate Interface in TANOS Stack Using Gate-Side Trap Spectroscopy by Charge Injection and Sensing

A statistical evaluation of current-voltage characteristics in small-size vertical poly-Si channels is used to study the poly-Si conduction properties and defects. Three poly-Si process options are considered. It is shown how defects and grain boundaries lead to percolation current paths, modulated by electron charging. Low mobility in microcrystalline-Si can be exchanged for higher mobility in large-grain poly-Si, at the expense of larger variability.

Statistical spectroscopy of switching traps in deeply scaled vertical poly-Si channel for 3D memories

We present carrier separation experiments based on direct charge measurement to assess the contributions of electrons and holes to the erase transient of TANOS-like nonvolatile memories. The role of different carrier species is analyzed as a function of erase voltage and charge configuration at the initial programmed state. We extend the analysis to band-engineered tunneling barriers, demonstrating that the performance improvement in these devices lies more on the enhancement of hole current rather than that of the electron one.

Statistical characterization of current paths in narrow poly-Si channels

We have demonstrated that the engineering of Si channel grains in vertical 3D devices is of tremendous importance for read current, leading to up to 10 times higher ID, 3 times steeper STS slope, tighter ID and STS distributions, better channel-oxide interface, less defective grain boundaries and larger memory window. LTA arises as a potential candidate to engineer the Si channel microstructure. The limitations of LTA regarding crystallization depth can be overcome through complementary techniques such as substrate heating assisted LTA. This learning is crucial for the successful fabrication of advanced vertical devices stacks.

Experimental Assessment of Electrons and Holes in Erase Transient of TANOS and TANVaS Memories

A characterization technique capable of measuring the electrical charge injected during programming operations in silicon nitride based charge trapping memories has been developed. The trapping efficiency, defined as the fraction of carriers which gets trapped in the device with respect to the total injected charge, is extracted and is evaluated along the programming transient for a wide set of devices, featuring different material deposition techniques and different thicknesses. The trapping efficiency is found to be almost insensitive to the injection conditions, whereas it depends on the quantity of filled traps, the thickness of the trapping layer and the conduction band offset between the trapping layer and the top oxide. A higher trapping efficiency in general leads to faster programming transients and more effective programming when increasing the gate voltage.

Laser thermal anneal of polysilicon channel to boost 3D memory performance

A new grain boundary model is proposed consisting of 1) a scattering part modeled by reduced mobility, independent of the microscopic details of the boundary, and 2) discrete randomly positioned charging defects. 2D and 3D model implementations are demonstrated, explaining several statistical properties in scaled poly-Si channel devices (particularly vertical NAND devices). In particular, we show that the temperature-dependent activation energy of the transconductance in a short channel poly-Si transistor is a statistical effect that can be modeled with a single grain boundary activation energy.