A. Furnemont

Root Cause of Charge Loss in a Nitride-Based Localized Trapping Memory Cell

Data retention loss mechanisms in nitride-based localized trapping memory devices are investigated with various electrical measurements and Medici simulations. First, the effect of program and erase cycles on device behavior is determined in terms of bottom oxide degradation and nitride charge profile evolution. Even if a strong degradation of the interface is observed, there is no important impact of this degradation on the cell behavior. However, the nitride charge profile evolves with cycling and leads to a three-pole electron-hole-electron profile over the channel region. Second, the interface trap annealing, the tunneling through the bottom oxide, and the lateral redistribution are studied in order to determine which mechanism plays the main role in the threshold voltage shift after cycling. The retention performance is dominated by a lateral redistribution of charges in the nitride layer.

Nitride Engineering for Improved Erase Performance and Retention of TANOS NAND Flash Memory

TANOS charge trap flash (CTF) with Al₂O₃-Si₃N₄-SiO₂ memory stack and TaN metal gate is a candidate technology to replace conventional floating gate technology for multi-level NAND applications beyond the 32nm node. The main drawbacks of TANOS to date are poor erase performance (in terms of speed and/or saturated level) as well as insufficient retention in the highest programmed state.

BEOL compatible high tunnel magneto resistance perpendicular magnetic tunnel junctions using a sacrificial Mg layer as CoFeB free layer cap

Perpendicularly magnetized MgO-based tunnel junctions are envisaged for future generation spin-torque transfer magnetoresistive random access memory devices. Achieving a high tunnel magneto resistance and preserving it together with the perpendicular magnetic anisotropy during BEOL CMOS processing are key challenges to overcome. The industry standard technique to deposit the CoFeB/MgO/CoFeB tunnel junctions is physical vapor deposition. In this letter, we report on the use of an ultrathin Mg layer as free layer cap to protect the CoFeB free layer from sputtering induced damage during the Ta electrode deposition. When Ta is deposited directly on CoFeB, a fraction of the surface of the CoFeB is sputtered even when Ta is deposited with very low deposition rates. When depositing a thin Mg layer prior to Ta deposition, the sputtering of CoFeB is prevented. The ultra-thin Mg layer is sputtered completely after Ta deposition. Therefore, the Mg acts as a sacrificial layer that protects the CoFeB from sputter-indu...

Physical Understanding of SANOS Disturbs and VARIOT Engineered Barrier as a Solution

Both read and program disturb sensitivity are identified to be major drawbacks for nitride-based NAND Flash arrays. The crucial aspects to understand the disturbs are the injection of electrons at low fields through the bottom oxide, and the tunneling through the top oxide during programming. These results are exploited to identify possible improvements of the device. A VARIOT engineered barrier is proposed to replace the bottom oxide layer in order to significantly reduce the disturb problem.

A Consistent Model for the SANOS Programming Operation

An accurate model for the SANOS programming operation has been developed. Excellent agreement between measurements and simulations in a large range of voltages and times is obtained, taking leakage through the gate stack and Frenkel-Poole detrapping into account. The model is exploited to predict the impact of the programming conditions on the retention behavior.

Physical Modeling of Retention in Localized Trapping Nitride Memory Devices

A physical model enabling accurate prediction of the retention in localized trapping nitride memory devices is presented first. The crucial components of this model are a correct observation of the charge distribution before and after cycling, and a thorough understanding of the charge detrapping and redistribution occurring in the nitride. The model is then validated for a large range of temperatures and number of cycles, and two different technologies. Finally, the results are exploited to identify the limiting factors of the retention loss, key for further improvement of nitride memory devices

Cycling behavior of nitride charge profile in NROM-type memory cells

Cycling of NROM-type memory cells leads to a dipolar distribution inside the nitride layer. This effect is due to a mismatch between hole and electron injected profiles resulting from conventional NROM operation. An extraction technique based on CP measurements allows the detailed observation of the mismatch. The proposed model explains the relation between the charge distributions and the cycling behavior which is experimentally confirmed by changing the programming and erasing conditions

Thin Co/Ni-based bottom pinned spin-transfer torque magnetic random access memory stacks with high annealing tolerance

Spin-transfer torque magnetic random access memory (STT-MRAM) is considered as a replacement for next generation embedded and stand-alone memory applications. One of the main challenges in the STT-MRAM stack development is the compatibility of the stack with CMOS process flows in which thermal budgets up to 400 °C are applied. In this letter, we report on a perpendicularly magnetized MgO-based tunnel junction (p-MTJ) on a thin Co/Ni perpendicular synthetic antiferromagnetic layer with high annealing tolerance. Tunnel magneto resistance (TMR) loss after annealing occurs when the reference layer loses its perpendicular magnetic anisotropy due to reduction of the CoFeB/MgO interfacial anisotropy. A stable Co/Ni based p-MTJ stack with TMR values of 130% at resistance-area products of 9 Ω μm2 after 400 °C anneal is achieved via moment control of the Co/Ta/CoFeB reference layer. Thinning of the CoFeB polarizing layer down to 0.8 nm is the key enabler to achieve 400 °C compatibility with limited TMR loss. Thinning the Co below 0.6 nm leads to a loss of the antiferromagnetic interlayer exchange coupling strength through Ru. Insight into the thickness and moment engineering of the reference layer is displayed to obtain the best magnetic properties and high thermal stability for thin Co/Ni SAF-based STT-MRAM stacks.

New Operating Mode Based on Electron/Hole Profile Matching in Nitride-Based Nonvolatile Memories

A new operating mode for the nitride-based nonvolatile memory cells using channel hot electron injection for programming and hot hole injection for erasing is presented. The mismatch between the injected electron and hole profiles during programming and erasing operations, which limits the performance of the device, can be prevented. The profiles, extracted from charge-pumping measurements, are tuned by changing the operating voltages in order to have matched distributions. Substantial improvements in endurance and subsequent high-temperature data retention are demonstrated

Statistical poly-Si grain boundary model with discrete charging defects and its 2D and 3D implementation for vertical 3D NAND channels

A new grain boundary model is proposed consisting of 1) a scattering part modeled by reduced mobility, independent of the microscopic details of the boundary, and 2) discrete randomly positioned charging defects. 2D and 3D model implementations are demonstrated, explaining several statistical properties in scaled poly-Si channel devices (particularly vertical NAND devices). In particular, we show that the temperature-dependent activation energy of the transconductance in a short channel poly-Si transistor is a statistical effect that can be modeled with a single grain boundary activation energy.