A. V. Pohm

The design of a one megabit non-volatile M-R memory chip using 1.5*5 mu m cells

A 10/sup 6/-bit chip has been designed using 1.5- mu m magnetoresistive double-layer memory elements and bipolar circuitry. The bipolar circuitry is based on nominal 1.25- mu m optical lithography. The total chip area of the design is 8.5 mm*9.5 mm. To enhance the signal-to-noise ratio, multiple reads are used with the nondestructive readout cells. Design read time is 3 mu s. Design write time is 0.2 mu s. The design includes three redundant, fuse-selectable sense lines for each group of 32 sense lines. If the bit failure rate is 0.0005 or less, yield loss for the 10/sup 6/-bit chip due to sense line failure is less than 19%. With improved lithography, elements as small as 0.75 mu m*2.5 mu m could be made from the material. >

New low current memory modes with giant magneto-resistance materials

Memory cells made with giant magnetoresistance (GMR) material have substantial differences in resistance for the two storage states even without the presence of sense current. Because of the large outputs, static memory cells requiring reduced currents can be made. Additional memory modes can be achieved because the resistance change depends on the angle between the magnetization in the two layers rather than the angle between the sense current and the magnetization. >

Magnetization in minimum geometry M-R heads with multilayer films

A one dimensional model has been developed for the distribution of magnetization in M-R elements; the model considers elements made from double layer films and those driven by a current through the elements. The model demonstrates that both demagnetizing and exchange effects must be taken into account as the elements are reduced to micron widths. The model also provides a convenient means for calculating average demagnetizing effects and magneto-resistive response.

High-density very efficient magnetic film memory arrays

Partially populated arrays using very small efficient DRO magnetic film memory cells have been constructed and tested to demonstrate the packaging and performance compatibility of such cells with integrated circuits. The experimental cells were made by vapor deposition of Permalloy, copper, and other materials through a mask in a flat wire configuration with an easy direction along the wire and a closed hard direction. A multiturn sense/digit line increased signal level and reduced drive current. cell densities from 4000 to 64 000 bit/in2have been examined. A typical cross section for an array consisted of 1200 A Permalloy films with 0.002-inch-wide word lines on 0.004-inch centers with five-turn digit lines on 0.015-inch centers (16 000 bit/in). Word currents for the 0.002-inch-wide word lines were typically 80 to 100 mA. Digit currents for the five-turn digit lines were typically 8 to 12 mA, and signal outputs were typically 5 to 7 mV with signals 15 ns in duration.

Dynamic switching process of sandwich-structured MR elements

The dynamic behavior of sandwich-structured magnetoresistive (MR) memory elements is studied analytically by solving Gilberts equation together with the one-dimensional micromagnetic torque equation. The typical element is 2 mu m*20 mu m and consists of two 150-AA thick magnetic layers separated by a 50-AA thick nonmagnetic layer. The easy axis is along the short dimension of the element. The theoretical study shows that wall nucleation is present when the switching is driven by a field applied in the easy-axis direction, whereas switching by a field in the hard-axis direction is accomplished by coherent rotation. The switching speed predicted by this one-dimensional model is in the nanosecond range and increases linearly with the external fields. >

2-dimensional numerical analysis of laminated thin film elements

A theoretical analysis of the laminated thin film elements is carried out by solving the micromagnetic equation. The boundary conditions of the equation are obtained by assuming that the magnetization is pinned at the edges of the elements. The dimension of the element is 2 mu m*20 mu m, with 150-AA-thick magnetic layers and a 50-AA-thick nonmagnetic layer. For the numerical analysis each magnetic layer is divided into 40*100 segments. The demagnetizing field is obtained by integrating the surface poles generated at the boundaries of the elements. Two different element shapes are considered: rectangular and diamond. Each shape is solved with its anisotropy constant either parallel or perpendicular to the long dimension of the element. >

10-35 Nanosecond magneto-resistive memories

It is known that M-R (magneto-resistive) memory elements possess the basic features necessary for a non-volatile, random access, read-write memory. Previous publications cited that an element size of 1.5 x 5 μm2 would need a read time of 3-5 μS because of the small signal level. These access times can be greatly reduced by increasing the element size in order to increase the signal level, and using a bridge formation in the read circuitry.

High speed (10-20 ns) non-volatile MRAM with folded storage elements

In magnetoresistive random access memories (MRAMs), the read access time is a function of cell size (aspect ratio). Thus it is possible to design MRAMs for a wide range of access times. A prototype MRAM chip has been designed using 250 Omega folded memory cells, two-turn word lines, and a high-speed differential sensing scheme. Simulation results indicate the total delay through the analog circuitry to be limited to 9.8 ns, thus demonstrating the MRAM access time to be within the range 10-20 ns. Even though the power consumption of the drive circuitry tends to be high when active, the nonvolatile nature of MRAMs makes them ideal for low-power applications. >

Analysis of M-R elements for 10/sup 8/ bit/cm/sup 2/ arrays

Magnetoresistive memory elements made from 100-AA thick, 65% Ni, 15% Fe, 20% Co layers separated by a 40-AA nonmagnetic layer have been analyzed theoretically. The analysis shows that with lithography capable of a minimum feature size of 0.4 mu m and with the ability to deposit nonconducting magnetic keepers, memory arrays with a density of 10/sup 8/ bit/cm/sup 2/ can be achieved. Analysis shows that such elements can lead to random access memories with an access time of 5 mu s. In the case of plated conducting keepers, the element density is slightly diminished. >

Properties of 1.4*2.8 mu m/sup 2/ active area M-R elements

Densely packed magnetoresistive memory cells with active areas of 1.4*2.8 mu m/sup 2/ have been studied experimentally and compared to larger 2.0*12 mu m/sup 2/ cells. The experimental results show that the smaller cells, although having smaller output voltages (0.3 mV), have about the same statistical distributions for critical parameters as the larger cells. Using the current nominal 1.2 mu m lithography prototype process, which adds one extra mask to the semiconductor processing, cells with an area of 12.6 mu m/sup 2/ are achieved. By adding another extra mask, the area can be reduced to 5.6 mu m/sup 2/. >