A. van der Werf

PHIDEO: a silicon compiler for high speed algorithms

PHIDEO is a silicon compiler targeted at the design of high performance real time systems with high sampling frequencies such as HDTV. It supports the complete design trajectory starting from a high level specification all the way down to layout. New techniques are used to perform global optimisations across loop boundaries in hierarchical flow graphs. The compiler is based on a new target architectural model. Apart from the datapaths special attention is paid to memory optimisation. The new techniques are demonstrated using a progressive scan conversion algorithm.<<ETX>>

Allocation of multiport memories for hierarchical data streams

A multiport memory allocation problem for hierarchical, i.e. multi-dimensional, data streams is described. Memory allocation techniques are used in high level synthesis for foreground and background memory allocation, the design of data format converters, and the design of synchronous inter-processor communication hardware. The techniques presented in this paper differ from other approaches in the sense that data streams are considered to be design entities and are not expanded to individual samples. A formal model for hierarchical data streams is given and a memory allocation algorithm is presented. The algorithm comprises two steps: data routing and assignment of signal delays to memories. A number of sub-problems are formulated as ILP programs. In the presented form, the allocation algorithm only considers interconnect costs, but memory size and other cost factors can be taken into account. The presented work is implemented in the memory allocation tool MEDEA which is part of the PHIDEO synthesis system.

Area optimization of multi-functional processing units

Functions executed by a multifunctional processing unit (PU) correspond to clusters of operations in the specification, which are represented as signal flow graphs (SFGs). Because of high-throughput demands, the operations of each SFG are executed in parallel. Since operations for only one of the SFGs are executed at a given time, operations belonging to different SFGs can be executed on the same operator. Here, the most important part of the mapping of several SFGs onto one PU, which is the assignment of the SFGs operations to the PUs operators, given a number of allocated operators, is considered. The problem is to find an operator assignment that minimizes the silicon area that is occupied by the PUs interconnection consisting of multiplexers and wires. An approach based on local search algorithms such as iterative improvement and simulated annealing is presented. Although these algorithms are known to be generally applicable, it is shown that detailed knowledge of the operator assignment problem is required to obtain good results within acceptable CPU time limits for large problem instances.<<ETX>>

Efficiency improvements for force-directed scheduling

Force-directed scheduling is a technique which schedules operations under time constraints in order to achieve schedules with a minimum number of resources. The worst case time complexity of the algorithm is cubic in the number of operations. This is due to the computation of the changes in the distribution functions needed for the force calculations. An incremental way to compute the changes in the distribution functions, based on gradual time-frame reduction, is presented. This reduces the time complexity of the algorithm to quadratic in the number of operations, without any loss in effectiveness or generality of the algorithm. Implementations show a substantial CPU-time reduction of force-directed scheduling, which is illustrated by means of some industrially relevant examples.<<ETX>>

I.McIC: a single-chip MPEG-2 video encoder for storage

MPEG2 encoding is done mainly by distributors and publishers using professional equipment too expensive for the consumer market. I.McIC is a video encoder for this market, in particular for storage applications where higher bit rates can he tolerated (5-15 Mb/s) compared with bit rates for transmission (1.5-8 Mb/s). I.McIC operates in MPEG ML@SP mode and offers good video quality at 5 Mb/s and excellent quality at 10 Mb/s. For consumer storage applications, the video signals to be encoded might not be as clean as typical studio standards. Therefore, noise reduction is an integral part of I.McIC. I.McIC can share 16 Mb DRAM with an MPEG2 video decoder, organized as 4 times 4 Mb devices with 60 ns access. It can handle both 50 Hz and 60 Hz video sources. To interface to a video source, I.McIC uses a line-locked clock generated by the A/D converter and running at 27 MHz.

Mpeg2 Video Encoding in Consumer Electronics

Only very recently, single-chip MPEG2 video encoders are being reported. They are a result of additional interest in encoding in consumer products, apart from broadcast encoding, where a video encoder contains several expensive chips. Only single-chip solutions are cost-effective enough to enable digital recording for the consumer. The professional broadcast encoders are expensive because they use the full MPEG toolkit to guarantee good image quality, at the lowest possible bit-rate. Some MPEG tools are costly in hardware and these are therefore not feasible in single-chip solutions. This results in higher bit-rates, that can be accepted because of the available channel and storage capacity of the latest consumer storage media, harddisk, digital tape (D-VHS) and Digital Versatile Disk (DVD). A consumer product is I.McIC, a single-chip MPEG2 video encoder. It operates in ML@SP mode which can be decoded by all MPEG2 decoders. The IC is highly-integrated, as it contains motion-estimation and compensation, adaptive temporal noise filtering and buffer/bit-rate control. The high-throughput functions of the MPEG algorithm are mapped onto pipelined dedicated hardware, whereas the remaining functions are processed by an application-specific instruction-set processor. Software for this processor can be downloaded, in order to suit the IC for different applications and operating conditions. The IC consists of several communicating processors which were designed using high-level synthesis tools, PHIDEO and DSP Station™.

Memory synthesis for high speed DSP applications

Describes technique for performing automatic memory allocation and address allocation for high-speed applications. Memory access conflicts are solved and a global strategy to merge memory units is presented. Efficient reuse of memory locations is obtained by the proposed address allocation techniques. The techniques are based on a stream model for describing data transport. As a specific application, the memory management of the PHIDEO silicon compiler is discussed.<<ETX>>

Relative location assignment for repetitive schedules

The authors point out that storage synthesis is becoming an important part of high-level synthesis. Emphasis is put on location assignment, i.e., the assignment of locations to variables in a storage unit. The technique of relative location assignment is discussed. This technique combines a fast algorithm (O(n log n)) with an efficient solution because at most one location more than the strict minimum is needed. As a consequence, the technique is particularly suited for large applications. This is illustrated using some real-life examples. The technique is implemented in a tool, called Matchbox, which is part of the Phideo synthesis system.<<ETX>>

Flexible datapath compilation for Phideo

Discusses design techniques for datapaths for video applications. Currently, PHIDEO, a silicon compiler for high speed algorithms, is being developed at the Philips Research Laboratories as part of SPRITE. Datapath compilation is one of the subtasks of this compiler. It will be shown that by including optimization tools like retiming, logic synthesis, and placement & routing the generators are less parametrized. Thereby the datapath compiler becomes more flexible.<<ETX>>

Architectural strategies for high-throughput applications

In this article an architecture is presented which allows efficient ASIC implementations of high throughput applications. Examples of these applications can be found in real time video applications such as EDTV, IDTV and HDTV. A key issue in the architecture is to provide a balance between memory resources and processing resources. Special attention is paid to the communication between these two types of resources. Architectural techniques are proposed to solve bottlenecks in the memory bandwidth and conflicts between memory accesses. Architectures for address generation in combination with location assignment are presented. The flexibility of the architectural model allows an efficient hardware realization on an ASIC exploiting the inherent parallelism of a particular application. This is illustrated in the article using a complex video algorithm for Progressive Scan Conversion. The proposed architecture is used as a target architecture which drives the high-level synthesis approach of the PHIDEO compiler.