Marco J. G. Bekooij

Efficient computation of buffer capacities for multi-rate real-time systems with back-pressure

A key step in the design of multi-rate real-time systems is the determination of buffer capacities. In our multi-processor system, we apply back-pressure as caused by bounded buffers in order to control jitter. This requires the derivation of buffer capacities that both satisfy the temporal constraints as well as constraints on the buffer capacity. Existing exact solutions suffer from the computational complexity associated with the required conversion from a multi-rate dataflow graph to a single-rate dataflow graph. In this paper we present an algorithm, with linear computational complexity, that does not require this conversion and that determines close to minimal buffer capacities. The algorithm is applied to an MP3 play-back application that is mapped on our network based multi-processor system.

Predictable Embedded Multiprocessor System Design

Consumers have high expectations about the video and audio quality delivered by media processing devices like TV-sets, DVD-players and digital radios. Predictable heterogenous application domain specific multiprocessor systems, which are designed around a networks-on-chip, can meet demanding performance, flexibility and power-efficiency requirements as well as stringent timing requirements. The timing requirements can be guaranteed by making use of resource management techniques and the analytical techniques that are described in this paper.

Dataflow analysis for real-time embedded multiprocessor system design

Dataflow analysis techniques are key to reduce the number of design iterations and shorten the design time of real-time embedded network based multiprocessor systems that process data streams. With these analysis techniques the worst-case end-to-end temporal behavior of hard real-time applications can be derived from a dataflow model in which computation, communication and arbitration is modeled. For soft real-time applications these static dataflow analysis techniques are combined with simulation of the dataflow model to test statistical assertions about their temporal behavior. The simulation results in combination with properties of the dataflow model are used to derive the sensitivity of design parameters and to estimate parameters like the capacity of data buffers.

A power-efficient single-chip OFDM demodulator and channel decoder for multimedia broadcasting

Orthogonal frequency division multiplex (OFDM) modulation makes possible heterogenous broadcasting networks in which satellites and terrestrial transmitters share the same frequency. A single-chip channel demodulator and decoder IC (DABchic) for consumer receiver products is based on the new digital audio broadcasting (DAB) standard. The challenging aspects in the design are: level of integration, silicon cost, design time, and power dissipation.

Performance guarantees by simulation of process

In this paper we derive the end-to-end temporal behavior of real-time applications that are described as process networks. We demonstrate that a tight upper bound on the arrival time of data can be derived by simulation of this process network. We also show that the effects of arbitration can be taken into account if resources are reserved. For an H263 video decoder example we derive by means of simulation the settings of the schedulers and the buffer capacities. We arrive at the conclusion that for this application a close to maximum throughput is obtained with small buffers if only one process is executed on each processor. Larger buffers are needed if processors are shared and processes are executed during long time-slices.

Phase coupled operation assignment for VLIW processors with distributed register files

The ever increasing complexity of signal processing applications and the desire to reduce the time to market demands efficient compilation techniques for programmable digital signal processors (DSPs). The paper describes constraint analysis based operation assignment techniques intended to deal with processors with distributed register files and partially connected networks. The assignment techniques have been implemented in our code generation tool FACTS (K. van Eijk et al., 2000). This tool is intended for the generation of an operation assignment, a register binding and a schedule of folded loops that satisfy the specified timing constraints. Our approach is based on satisfaction of constraints which makes it different from optimisation based operation assignment techniques. The operation assignment technique is based on the modeling of the assignment search space in a conflict graph. Pruning of this conflict graph prevents decisions that inevitably lead to solutions that do not satisfy the timing constraints. If after pruning, infeasibility is detected, backtracking of assignment decisions is performed. In order to obtain a tight coupling between the assignment phase and the schedule phase, information is derived from the conflict graph which is used to prune the schedule search space, and information from the schedule search space is incorporated in the conflict graph. Automatic insertion of copy operations for moving intermediate values from one register file to another register file is not supported. However the use of a shared global bus in the processor guarantees that at least one direct communication path from a producing functional unit to a consuming functional unit exists and therefore the use of copy operations is not necessary.

Functional units with conditional input/output behavior in VLIW processors

Summary form only given. In this paper we extend the method to deal with coarse-grain operations in static scheduled VLIW processors as is introduced by Busa (2000). We allow functional units with a controller that does not traverse its states in a predefined way. This makes it possible to execute a function that contains a conditional construct like an if-statement as a single operation on a functional unit. In this way the performance penalty otherwise caused by branch instructions is reduced. By adding valid input and output signals, the problem is circumvented that during compilation it is, for this type of functional unit, not known when and how many samples will be consumed or produced. We refer to these units as Conditional Input/output Units (CIUs). The operations that are executed on CIUs are called Conditional Input/output Operations (CIOs). The difference with guarded operations is that the production of a result of a CIO depends on the state of the CIU.