J. van Meerbergen

Networks on Silicon: Combining Best-Effort and Guaranteed Services

We advocate a network on silicon (NOS) as a hardware architecture to implement communication between IP cores in future technologies, and as a software model in the form of a protocol stack to structure the programming of NOSs. We claim guaranteed services are essential. In the ETHEREAL NOS they pervade the NOS as a requirement for hardware design, and as foundation for software programming.

PHIDEO: a silicon compiler for high speed algorithms

PHIDEO is a silicon compiler targeted at the design of high performance real time systems with high sampling frequencies such as HDTV. It supports the complete design trajectory starting from a high level specification all the way down to layout. New techniques are used to perform global optimisations across loop boundaries in hierarchical flow graphs. The compiler is based on a new target architectural model. Apart from the datapaths special attention is paid to memory optimisation. The new techniques are demonstrated using a progressive scan conversion algorithm.<<ETX>>

Allocation of multiport memories for hierarchical data streams

A multiport memory allocation problem for hierarchical, i.e. multi-dimensional, data streams is described. Memory allocation techniques are used in high level synthesis for foreground and background memory allocation, the design of data format converters, and the design of synchronous inter-processor communication hardware. The techniques presented in this paper differ from other approaches in the sense that data streams are considered to be design entities and are not expanded to individual samples. A formal model for hierarchical data streams is given and a memory allocation algorithm is presented. The algorithm comprises two steps: data routing and assignment of signal delays to memories. A number of sub-problems are formulated as ILP programs. In the presented form, the allocation algorithm only considers interconnect costs, but memory size and other cost factors can be taken into account. The presented work is implemented in the memory allocation tool MEDEA which is part of the PHIDEO synthesis system.

Analysis and reduction of glitches in synchronous networks

The influence of transition activity on dynamic power dissipation is analysed by examining three components: dissipation in combinational logic, flipflops and clock line. Transition activity is analysed by making a distinction between useful transitions and glitches (useless transitions). A transition counting and parity evaluation method is used for this. Most glitches can be eliminated by introducing flipflops using retiming and pipelining and/or by choosing different architectures. In this way an optimal level for pipelining can be found.<<ETX>>

Stream communication between real-time tasks in a high-performance multiprocessor

The demands in terms of processing performance, communication bandwidth and real-time throughput of many multimedia applications are much higher than todays processing architectures can deliver. The PROPHID heterogeneous multiprocessor architecture template aims to bridge this gap. The template contains a general purpose processor connected to a central bus, as well as several high-performance application domain specific processors. A high-throughput communication network is used to meet the high bandwidth requirements between these processors. In this network multiple time-division-multiplexed data streams are transferred over several parallel physical channels. This paper presents a method for guaranteeing the throughput for hard-real-time streams in such a network. At compile time sufficient bandwidth is assigned to these streams. The assignment can be determined in polynomial time. Remaining bandwidth is assigned to soft-real-time streams at run time. We thus achieve efficient stream communication with guaranteed performance.

The Sprite Input Language-an intermediate format for high level synthesis

Describes a simple and powerful input language (intermediate format) for high level synthesis. The language belongs to the class of signalflow graphs. The Sprite Input Language (SIL) encompasses both the applicative constructs on which classical DSP languages like Silage are based, the functional constructs from hardware description languages like ELLA, and the operational constructs from sequential languages like Pascal and C. This is obtained by means of the single token flow model and using sets instead of single values for data modelling. The language is suited for acting as an intermediate language between the various specification languages and the silicon compilation system, as well as a language backbone in the synthesis part of a silicon compiler.<<ETX>>

Area optimization of multi-functional processing units

Functions executed by a multifunctional processing unit (PU) correspond to clusters of operations in the specification, which are represented as signal flow graphs (SFGs). Because of high-throughput demands, the operations of each SFG are executed in parallel. Since operations for only one of the SFGs are executed at a given time, operations belonging to different SFGs can be executed on the same operator. Here, the most important part of the mapping of several SFGs onto one PU, which is the assignment of the SFGs operations to the PUs operators, given a number of allocated operators, is considered. The problem is to find an operator assignment that minimizes the silicon area that is occupied by the PUs interconnection consisting of multiplexers and wires. An approach based on local search algorithms such as iterative improvement and simulated annealing is presented. Although these algorithms are known to be generally applicable, it is shown that detailed knowledge of the operator assignment problem is required to obtain good results within acceptable CPU time limits for large problem instances.<<ETX>>

Efficiency improvements for force-directed scheduling

Force-directed scheduling is a technique which schedules operations under time constraints in order to achieve schedules with a minimum number of resources. The worst case time complexity of the algorithm is cubic in the number of operations. This is due to the computation of the changes in the distribution functions needed for the force calculations. An incremental way to compute the changes in the distribution functions, based on gradual time-frame reduction, is presented. This reduces the time complexity of the algorithm to quadratic in the number of operations, without any loss in effectiveness or generality of the algorithm. Implementations show a substantial CPU-time reduction of force-directed scheduling, which is illustrated by means of some industrially relevant examples.<<ETX>>

Automated synthesis of a high speed Cordic algorithm with the Cathedral-III compilation system

The automated design methodology of the Cathedral-III system is presented. The Cathedral-III system is an environment for efficient synthesis of high-throughput digital-signal-processing circuits. The system translates a behavioral description, expressed in the Silage language, into an intermediate signal flow graph representation, which is assembled and optimized into a dedicated bit-sliced architecture. The Cordic algorithm is used as test-vehicle to demonstrate the features of the Cathedral-III methodology.<<ETX>>

Automatic synthesis of signal processing benchmark using the CATHEDRAL silicon compilers

A discussion is presented of implementation of two WDF (wave digital filter) benchmarks that have been designed with three architecture-specific silicon compilers. The design time for high-level synthesis and optimization is roughly one day. For each of the three synthesis systems, the elapsed design cycle starting from the specifications down to the optimized signal flow graph is another 1-2 days. For the architecture and layout generation (including the evaluation of the tradeoffs), the design time ranges from a few hours to a day. Specific higher-level filter specifications have been used for the synthesis with three different implementation strategies in the CATHEDRAL silicon compilers. It is shown that as an initial optimization step, it is important to initially choose a good algorithm.<<ETX>>