A.W.S. Ross
University of Edinburgh
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Publication
Featured researches published by A.W.S. Ross.
IEEE Transactions on Semiconductor Manufacturing | 2002
Stewart Smith; Anthony J. Walton; A.W.S. Ross; G. Bodammer; J.T.M. Stevenson
The effects of the barrier layer and dishing in copper interconnects lead to extra difficulties in measuring sheet resistance (R/sub S/) and linewidth when compared with equivalent measurements on nondamascene tracks. This paper examines these issues and presents the results of simulations that quantify the effects of diffusion barrier layers and dishing on the extraction of R/sub S/ from cross type test structures and the effect this has on linewidth measurement.
IEEE Transactions on Semiconductor Manufacturing | 2003
Stewart Smith; Anthony J. Walton; S. Bond; A.W.S. Ross; J.T.M. Stevenson; A.M. Gundlach
Focused ion beam (FIB) systems are commonly used to image, repair and modify integrated circuits by cutting holes in passivation to create vias or to selectively break metal tracks. The ion beam can also be used to deposit a metal, such as platinum, to create new connections. These techniques are very useful tools for debugging designs and testing possible changes to the circuit without the expense of new mask sets or silicon. This paper presents test structures which can be used to characterize a FIB induced platinum deposition process. Sheet resistance test structures have been fabricated using a FIB tool and the results of testing these structures are presented. The sheet resistance data has been used to fabricate platinum straps with a known resistance. This extends the capability of the focused ion beam system beyond the deposition of simple conducting straps. The design of the test structures has been improved through the use of current flow simulation to investigate the effects of geometry and misalignment on the measurement accuracy. The results of these simulations are also presented.
international conference on microelectronic test structures | 2005
Stewart Smith; Anthony J. Walton; M. McCallum; A.C. Hourd; J.T.M. Stevenson; A.W.S. Ross
Electrical test structures have been designed that are compatible with a standard alternating aperture, phase-shift mask manufacturing process. Measurements indicate that these have superior performance to previous designs where Greek cross structures suffered from asymmetry problems. As a result, the new test structures extract a consistent, and accurate, sheet resistance. In addition, the measurements on linewidth structures have demonstrated an improved capability with the CD offset variability being reduced to a quarter of the previous value. Electrical CD results from a wide range of test structures, both phase-shifted and binary, are presented and it is demonstrated that the phase-shifting elements have a negligible effect on the measurements. A limited number of atomic force microscope measurements have also been made for comparison purposes.
international conference on microelectronic test structures | 2004
Stewart Smith; Martin McCallum; Anthony J. Walton; J.T.M. Stevenson; Paul D. Harris; A.W.S. Ross; Andrew C. Hourd; Liudi Jiang
The ability to test and characterise advanced photomasks for verification and process control is increasingly important and this paper builds on previous work in this area. Atomic force and scanning electron microscope measurements are used to explain anomalies in previously presented results. In addition, a new test structure has been developed to measure an important parameter in alternating aperture phase shifting masks: the alignment between the chrome blocking features and the phase shifting regions etched into the quartz substrate. Simulation results are presented which demonstrate the capability of the test structure when used in a progressional offset array.
international conference on microelectronic test structures | 2001
Stewart Smith; Anthony J. Walton; A.W.S. Ross; G. Bodammer; J.T.M. Stevenson
The effect of the barrier layer and dishing in copper interconnects causes extra difficulties in measuring sheet resistance and linewidth when compared with equivalent measurements on nondamascene processed tracks. This paper examines these issues and, for the first time, quantifies the effects of diffusion barrier layers and CMP dishing on the extraction of R/sub s/ from Greek cross type structures and the effect this has on linewidth measurement.
IEEE Transactions on Semiconductor Manufacturing | 2008
Byron J. R. Shulver; Andrew Bunting; A.M. Gundlach; Les I. Haworth; A.W.S. Ross; Stewart Smith; A.J. Snell; J.T.M. Stevenson; Anthony J. Walton; Richard A. Allen; Michael W. Cresswell
Test structures have been fabricated to allow electrical critical dimensions (ECD) to be extracted from copper features with dimensions comparable to those replicated in integrated circuit (IC) interconnect systems. The implementation of these structures is such that no conductive barrier metal has been used. The advantage of this approach is that the electrical measurements provide a nondestructive and efficient method for determining critical dimension (CD) values and for enabling fundamental studies of electron transport in narrow copper features unaffected by the complications of barrier metal films. This paper reports on the results of tests which have been conducted to evaluate various extraction methods for sheet resistance and line width values from the current design.
international conference on microelectronic test structures | 2002
Stewart Smith; Anthony Walton; S. Bond; A.W.S. Ross; J.T.M. Stevenson; A.M. Gundlach
Focused Ion Beam (FIB) systems are commonly used to image, repair and modify integrated circuits by cutting holes in passivation to create vias or to selectively break metal tracks. The ion beam can also be used to deposit a metal, such as platinum, to create new connections. These techniques are very useful tools for debugging designs and testing possible changes to the circuit without the expense of new mask sets or silicon. This paper presents test structures to characterise a FIB platinum deposition process. Sheet resistance test structures have been fabricated using a FIB tool and the results of testing these structures are presented. This data will enable resistors with a known value to be fabricated in addition to conducting straps.
Micro-Opto-Electro-Mechanical Systems | 2000
A.W.S. Ross; Stephen C. Graham; A.M. Gundlach; J. Tom M. Stevenson; William J. Hossack; David G. Vass; G. Bodammer; Euan Smith; Kevin Ward
We describe the fabrication and testing of deformable membrane mirrors over silicon backplanes using our in-house CMOS processing facilities. The fabrication of dense arrays of electrostatic actuators on the backplane potentially allows fine control of the membrane surface shape than can be produced when using a printed circuit board as the backplane. We presents a range of techniques for fabrication the membrane mirrors in various materials and mating the structure to a silicon backplane. We characterise membrane deflection with electric field for silicon nitride and polymer membranes over a passive silicon backplane consisting of 37 directly-addressed electrode pads configured in a hexagonal array.
international conference on microelectronic test structures | 2007
Byron J. R. Shulver; Andrew Bunting; A.M. Gundlach; Les I. Haworth; A.W.S. Ross; Stewart Smith; A.J. Snell; J.T.M. Stevenson; Anthony J. Walton; Richard A. Allen; Michael W. Cresswell
Test structures have been fabricated to allow electrical critical dimensions (ECD) to be extracted from copper features with dimensions comparable to those replicated in IC interconnect systems. The implementation of these structures is such that no conductive barrier metal has been used. The advantage of this approach is that the electrical measurements provide a non-destructive and efficient method for determining CD values and for enabling fundamental studies of electron transport in narrow copper features unaffected by the complications of barrier metal films. This paper reports on the results of various tests which have been conducted to evaluate the current design.
international conference on microelectronic test structures | 2005
S. Enderling; C.L. Brown; Stewart Smith; M.H. Dicks; J.T.M. Stevenson; A.W.S. Ross; Maria Mitkova; Michael N. Kozicki; Anthony J. Walton
A novel method is reported to measure the sheet resistance of materials that are incompatible with a CMOS process, using suspended polysilicon Greek cross test structures. To demonstrate the technique, gold (Au) was blanket evaporated in various thicknesses onto the test structures and the sheet resistance extracted. Sheet resistances ranging from 0.30/spl Omega///spl square/to 0.10/spl Omega///spl square/were measured for the deposited Au films on Greek cross structures with arm widths ranging between 5 and 20 /spl mu/m. The extracted resistivity of 4.85/spl times/10/sup -8//spl Omega/m agrees with values found in the literature (3.0/spl times/10/sup -8//spl Omega/m-5.0/spl times/10/sup -8//spl Omega/m) demonstrating that the structures are fully capable of measuring sheet resistance of blanket deposited films.