J.T.M. Stevenson

Room-Temperature Fabrication of Anodic Tantalum Pentoxide for Low-Voltage Electrowetting on Dielectric (EWOD)

This paper presents a robust anodic Ta2O5 dielectric as an alternative insulator for fabricating low-voltage electrowetting on dielectric (EWOD) systems. Previously reported low-voltage EWOD technologies require high-temperature processes ( > 435degC), which unlike this room temperature technology, are not compatible with standard copper and aluminum integrated circuit interconnect technology as well as polymer-based substrates. The anodized Ta2O5 forms a uniform pinhole free layer with a surface roughness (R a) of 0.6 nm. This robust film enables an ultrathin amorphous FluoroPolymer layer to be employed to reduce the EWOD driving voltage to 13 V. Both sub-20-nm Teflon-AF and CYTOP layers have been successfully coated on top of Ta2O5 with good adhesion. Applying voltages of 6-15 V significantly modified the contact angles of droplets in air on these samples (121deg to 81deg on Teflon-AF at 13 V and 114deg to 95deg on CYTOP at 6 V). Successful 14-V EWOD manipulation involving droplets being dispensed from a reservoir, their movement, followed by merging them together has been demonstrated using devices using a Teflon-AF + Ta2O5 dielectric.

Sheet resistance measurement of non-standard cleanroom materials using suspended Greek cross test structures

This paper presents work on the development, fabrication and characterization of a suspended Greek cross measurement platform that can be used to determine the sheet resistance of materials that would contaminate Complementary Metal Oxide Semiconductor (CMOS) processing lines. The arms of the test structures are made of polysilicon/silicon nitride (Si/sub 3/N/sub 4/) to provide a carrier for the film to be evaluated and thick aluminum (Al) probe pads for multiple probing. The film to be evaluated is simply blanket deposited onto the structures and because of its design automatically forms a Greek cross structure with (Al) probe pads. To demonstrate its use, 1) gold (Au), 2) copper (Cu), and 3) silver(Ag) loaded chalcogenide glass Ag/sub y/(Ge/sub 30/Se/sub 70/)/sub 1-y/ have been blanket evaporated in various thicknesses onto the platform in the last processing step and autopatterned by the predefined shape of the Greek crosses. The suspension of the platform ensured electrical isolation between the test structure and the surrounding silicon (Si) substrate. The extracted effective resistivity for Au (5.1/spl times/10/sup -8/ /spl Omega//spl middot/m), Cu (1.8- 2.5/spl times/10/sup -8//spl bsol/ /spl Omega//spl middot/m) and Ag/sub y/(Ge/sub 30/Se/sub 70/)/sub 1-y/ (2.27/spl times/10/sup -5/ /spl Omega//spl middot/m-1.88 /spl Omega//spl middot/m) agree with values found in articles in the Journal of Applied Physics (1963), the Journalof Physics D: Applied Physics (1976), and the Journalof Non-Crystalline Solids (2003). These results demonstrate that the proposed Greek cross platform is fully capable to measure the sheet resistance of low (Au, Cu) and high Ag/sub y/(Ge/sub 30/Se/sub 70/)/sub 1-y/ resistive materials.

Evaluation of sheet resistance and electrical linewidth measurement techniques for copper damascene interconnect

The effects of the barrier layer and dishing in copper interconnects lead to extra difficulties in measuring sheet resistance (R/sub S/) and linewidth when compared with equivalent measurements on nondamascene tracks. This paper examines these issues and presents the results of simulations that quantify the effects of diffusion barrier layers and dishing on the extraction of R/sub S/ from cross type test structures and the effect this has on linewidth measurement.

A novel approach for reducing the area occupied by contact pads on process control chips

An approach which reduces the number of pads required by electrical test structures is presented. The multiplexed scheme requires only two levels of interconnect and enables more devices to be located in a given area, providing the designer of test structures with more freedom to experiment with structures previously requiring a large number of pads. Applications for transistors, electrical verniers, yield monitoring, reliability evaluations, continuity tests, and measuring the resistance of tracks are discussed.<<ETX>>

Comparison of electrical and SEM CD measurements on binary and alternating aperture phase-shifting masks

Many of the recent advances in optical lithography have been driven by the utilization of complex photomasks using optical proximity correction (OPC) or phase-shifting technologies. These masks are difficult and expensive to manufacture so the ability to test and characterize the mask making process is very important. This paper examines the issues involved in the use of relatively low-cost electrical critical dimension (ECD) measurement of mask features. Modified cross-bridge test structures have been designed to allow the on-mask measurement of dense and isolated, binary and phase-shifted layouts. The results of electrical and critical dimension scanning electron microscope (CD-SEM) testing of these structures are presented and indicate the lower variability associated with ECD measurements. In particular the adverse effect of phase-shifting elements on the accuracy of SEM measurements is highlighted.

Dependence of process parameters on stress generation in aluminum thin films

The dependence of residual stress on the process parameters for aluminum metallization has been studied using a rotating beam sensor. This shows increasing tensile stress with both the target power and ambient pressure used during the sputter deposition of the aluminum layer. The bulk resistivity of the deposited aluminum has been measured using a Van der Pauw technique on test structures fabricated alongside the sensors and this shows different trends with respect to the target power and ambient pressure. This indicates that the stress in an interconnect feature is dominated by extrinsic components, which result from the mismatch in thermal expansion coefficient between the constituent layers, rather than the defects formed during the sputter deposition of the metallization. This indicates the suitability of the stress sensor technique to the monitoring of interconnect features in a production line environment.

Electrical characterization of platinum deposited by focused ion beam

Focused ion beam (FIB) systems are commonly used to image, repair and modify integrated circuits by cutting holes in passivation to create vias or to selectively break metal tracks. The ion beam can also be used to deposit a metal, such as platinum, to create new connections. These techniques are very useful tools for debugging designs and testing possible changes to the circuit without the expense of new mask sets or silicon. This paper presents test structures which can be used to characterize a FIB induced platinum deposition process. Sheet resistance test structures have been fabricated using a FIB tool and the results of testing these structures are presented. The sheet resistance data has been used to fabricate platinum straps with a known resistance. This extends the capability of the focused ion beam system beyond the deposition of simple conducting straps. The design of the test structures has been improved through the use of current flow simulation to investigate the effects of geometry and misalignment on the measurement accuracy. The results of these simulations are also presented.

Electrical CD characterisation of binary and alternating aperture phase shifting masks

Many of the recent advances in optical lithography have been driven by the utilisation of complex photomasks using Optical Proximity Correction (OPC) or phase shifting technologies. These masks are difficult and expensive to manufacture so the ability to test and characterise the mask making process is very important. This paper examines the issues involved in the use of relatively low cost Electrical Critical Dimension (ECD) measurement of mask features. Modified cross-bridge test structures have been designed to allow the on-mask measurement of dense and isolated, binary and phase shifted layouts. The results of electrical and Critical Dimension Scanning Electron Microscope (CD-SEM) testing of these structures are presented and indicate the lower variability associated with ECD measurements. In particular the adverse effect of phase shifting elements on the accuracy of SEM measurements is highlighted.

Test chip for the development and evaluation of sensors for measuring stress in metal interconnects

The development of a new test chip is presented, containing structures for the direct measurement of stress in metallic interconnect layers associated with silicon integrated circuit technology. The rotation of the structures provides a simple method of differentiating between tensile and compressive stress. This test chip design has been used to fabricate working structures allowing the study of stresses in aluminum layers before and after sample sintering. The results are presented together with the design, fabrication, and measurement considerations that have arisen during the research. The problems experienced in removing the sacrificial layer material, necessary to release the structures, are discussed along with potential solutions. The sensor structure is suitable for fabrication within a CMOS facility and its inherent scalability makes it potentially suitable for in-line testing of state-of-the-art processes.

Fabrication and Measurement of Test Structures to Monitor Stress in SU-8 Films

SU-8 is an epoxy-based, negative photoresist that is widely used in the manufacturing of micromechanical systems. The polymer cross-linking that occurs during the photolithographic processing of SU-8 can result in high levels of stress in the patterned film. This has significant implications for the yield and reliability of SU-8 structures and needs to be understood if the material is to be integrated with other technologies. This paper describes micromechanical test structures that provide the opportunity to wafer map the stress in SU-8 at different stages of the process. The structures are fabricated in a thick layer of SU-8 and are subsequently released from the underlying substrate using a dry chemical vapor etch process. An automated optical measurement system has been built to allow rapid optical inspection of many thousands of test structures fabricated on 200 mm wafers. Initial results indicate significant tensile stress in the SU-8, which demonstrates a radial variation along with a dependence on the process conditions.