A. Wurz

MULTIPROCESSOR AND MEMORY ARCHITECTURE OF THE NEUROCOMPUTER SYNAPSE-1

A general purpose neurocomputer, SYNAPSE-1, which exhibits a multiprocessor and memory architecture is presented. It offers wide flexibility with respect to neural algorithms and a speed-up factor of several orders of magnitude--including learning. The computational power is provided by a 2-dimensional systolic array of neural signal processors. Since the weights are stored outside these NSPs, memory size and processing power can be adapted individually to the application needs. A neural algorithms programming language, embedded in C(+2) has been defined for the user to cope with the neurocomputer. In a benchmark test, the prototype of SYNAPSE-1 was 8000 times as fast as a standard workstation.

Concept of the first level trigger for HERA-B

The HERA-B detector aims to measure CP violation in the B meson system. The B mesons under study are produced in interactions of 820 CeV/c protons with the fixed target. Together with the B mesons a 6 orders of magnitude larger background of minimum bias interactions is produced. A highly selective and efficient trigger system is required and has been designed to acquire a sufficient amount of signal decays. It is able to find lepton and hadron tracks and reconstruct their kinematics on the first level of the trigger chain. The final first level trigger decision is based on the properties of the reconstructed pair of tracks. This is mainly targeting at J//spl psi//spl rarr/l/sup +/l/sup -/ and B/sup 0//spl rarr//spl pi//sup +//spl pi//sup -/ signatures. A parallel and pipelined system of approximately 100 processors is designed to perform this job. It reduces a 10 MHz input rate by a factor of 200 with a latency of 5 to 10 /spl mu/s. A special detailed simulation package was designed to study the system performance and prove the algorithms used. Being a constituent part of the general HERA-B software, it provides not only the possibility of trigger studies but also selects FLT-passing events to be considered as input stream for the studies of the following levels of the HERA-B trigger system.

SYNAPSE-1: a high-speed general purpose parallel neurocomputer system

The paper describes the general purpose neurocomputer SYNAPSE-1 which has been developed in cooperation between Siemens Munich and the University of Mannheim. This system contains one of the most powerful processors available for neural algorithms, the neuro signal processor MA16. The prototype system executes a test algorithm 8000 times as fast as a Sparc-2 workstation. This processing speed has been achieved by using a system architecture which is optimally adapted to the general structure of neural algorithms. It is a systolic array of MA16 processors embedded in a multiprocessor system of general purpose microprocessors.<<ETX>>

Design of the HERA-B first level trigger

The HERA-B first level trigger (FLT) mainly identifies lepton pairs from J//spl psi/ decays. It reduces a 10 MHz input rate by a factor of 200 with a mean latency of /spl ap/5 /spl mu/s. The FLT is a hardware processor consisting of track finding units (TFUs), track parameter units (TPUs), and a trigger decision unit (TDU). Tracking chamber data are transferred at a rate of /spl ap/600 Gbit/s into memories distributed over the TFUs. 12 serial link chips, each providing a bandwidth of 1.8 Gbit/s, will be used per TFU. Between 4 and 14 TFUs are assigned to different sections of each layer of tracking chambers so that their load is balanced. In total 60 TFUs are used to equip the 7 tracking layers. For the current bunch crossing, a coincidence matrix identifies track hits in the search region using 3 stereo views of the assigned tracking chamber section. The improved search region, extrapolated to the next tracking chamber superlayer, is read from a lookup table and transmitted to one or more TFUs assigned to the next superlayer. If the track is followed through all tracking chambers the last TFU communicates the track parameters to a TPU. The TPU determines from the transmitted track information the kinematic parameters of the lepton candidate to accept or reject it. Finally the tracks of the same event are collected in the TDU. It computes the invariant mass of track pairs to make the final trigger decision. The system is in the board layout stage. Prototype testing is scheduled for begin of 1996.

Multiprozessor- und Speicher-Architektur des Neurocomputer SYNAPSE-1

Um den Zeitaufwand fur die Entwicklung neuronaler Applikationen verringern und die Anwendungsforschung weiter vorantreiben zu konnen, hat ZFE den Neurocomputer SYNAPSE-1 gebaut. SYNAPSE-1 bezieht seine Leistungsfahigkeit (peak performance 5,1 · 109 Verbindungen bzw. Multiplikationen und Additionen pro Sekunde) aus einer skalierbaren Multi-Prozessor- und -Speicherarchitektur und aus dem selbst entwickelten Neuro-Signalprozessor MA16 (full custom VLSI, 1μm CMOS, 610 000 Transistoren), welcher die rechenintensiven Operationen der neuronalen Algorithmen ausfuhrt. SYNAPSE-1 besteht hardwareseitig aus 4 Boards: einem mit 8 MA16 bestuckten Board, einem ’Data Unit’-Board, welches die restlichen, nicht-rechenintensiven neuronalen Operationen ausfuhrt, einer Speicherplatine hoher Bandbreite fur die Gewichte und einer Controller-Platine fur Steuerung und Koordination der anderen Boards. Die Kommunikation mit Host-Workstation und spezialisierten Ein-/Ausgabeeinheiten (z.B. frame grabber) wird von Controller und Data Unit uber den VME-Bus abgewickelt (Data und Control Unit wurden in Kooperation mit Prof. Manner, Universitat Mannheim, entwickelt).