Alexander Gröpl

Latency-and hazard-free volume memory architecture for direct volume rendering

The computational power required for direct volume rendering like ray-casting or volume ray-tracing can be provided by highspeed rendering architectures. However the increasing processor speed makes a performance bottleneck obvious - the volume memory. This paper describes a volume memory architecture that achieves at least a tenfold speed-up in read-out rate with moderate additional hardware. It has been simulated successfully. A multi-level cache system is used with software prefetching and latency hiding. Pre- and postcaches additionally speed up the read-out rate so that a 5123 data set stored in a single memory module can be rendered at 3.125 Hz.

Concept of the first level trigger for HERA-B

The HERA-B detector aims to measure CP violation in the B meson system. The B mesons under study are produced in interactions of 820 CeV/c protons with the fixed target. Together with the B mesons a 6 orders of magnitude larger background of minimum bias interactions is produced. A highly selective and efficient trigger system is required and has been designed to acquire a sufficient amount of signal decays. It is able to find lepton and hadron tracks and reconstruct their kinematics on the first level of the trigger chain. The final first level trigger decision is based on the properties of the reconstructed pair of tracks. This is mainly targeting at J//spl psi//spl rarr/l/sup +/l/sup -/ and B/sup 0//spl rarr//spl pi//sup +//spl pi//sup -/ signatures. A parallel and pipelined system of approximately 100 processors is designed to perform this job. It reduces a 10 MHz input rate by a factor of 200 with a latency of 5 to 10 /spl mu/s. A special detailed simulation package was designed to study the system performance and prove the algorithms used. Being a constituent part of the general HERA-B software, it provides not only the possibility of trigger studies but also selects FLT-passing events to be considered as input stream for the studies of the following levels of the HERA-B trigger system.

Latency- and hazard-free volume memory architecture for direct volume rendering

Abstract Real-time direct volume rendering (ray-casting or volume ray-tracing) is achieved by problem specific rendering architectures. The performance of these architectures is however limited by the access to the volume memory. Although many different volume memory architectures have been proposed and realized, none of them uses the read-out-gain provided by new DRAM interfaces like Rambus-DRAM, SDRAM etc . In this paper a solution is presented that allows profit from these new interfaces. The key feature of the new architecture is a multi-level cache system with software prefetching and latency hiding. By allowing the rendering pipeline processor to operate at up to 200 MHz, a 512 3 data set stored in a single memory module can be rendered at 3.125 Hz. An even higher performance is possible from the DRAM side but is limited by current SRAM and processor speeds.

Evaluation of a real-time direct volume rendering system

VIRIM, a real-time direct volume rendering system is evaluated for medical applications. Experiences concerning the hardware architecture are discussed. The issues are the flexibility of VIRIM, the restriction to two gradient components only, the duplication of the volume data sets on different modules, the size of the volume data set, the gray-value segmentation tool, and the support of algorithmic improvements like space-leaping, early ray-termination and others. It turned out that flexibility is the main benefit and absolutely necessary for VIRIM. Given this flexibility the application areas of real-time rendering systems increase dramatically: Most of the user requirements focus now not on visualization but on general volume data processing. The most serious bottleneck of VIRIM is the limited volume memory that is integrated on the first prototype. The most frequently used tool of VIRIM is gray-value segmentation. It is highly useful if original, i.e. unsegmented data have to be dealt with, and if pre-segmented data have to be investigated. All other benefits and architectural shortcomings are not critical for the application areas of VIRIM, i.e. operation simulation and control in head surgery.

A Volume Rendering Crossbar and SRAM-Based Hardware

Volume data acquired by different imaging systems is best visualised through volume rendering [1] approaches if semi-transparency and avoidance of surface generation is imperative. Available algorithms include ray casting [2] and shadowing approaches such as the Heidelberg ray tracer [3]. Hardware architectures for real-time rendering are, among others, VIRIM [4], Cube-4 [5], and VIZZARD [6] (see also Section 1.14). The systems depend on either special-purpose chips, FPGAs or DSP processors.