A. Yu. Matrosova

Self-checking Synchronous FSM Network Design with Low Overhead

A method of a self-checking synchronous Finite State Machine (FSM) network design with low overhead is developed. Checkers are used only for FSMs, which output lines are at the same time output lines of the network. The checkers observe output lines of these FSMs. The method is based on reducing the problem to a self-checking synchronous FSM design. The latter is provided by applying a special description of FSM namely, so-called unate Programmable Logic Array (PLAu) description. Single stuck-at fault on the FSM poles and gate poles are considered. PLA realization ofFSM allows a factorized or multilevel logic synthesis. They both provide a unidirectional manifestation of the above mentioned faults on the output lines of the corresponding FSMs. This realization also gives rise to a transparency of each component FSM of the network for the faults. PLA realization is derived from the State Transition Graph (STG) description of FSMs with using the m-out-of-n encoding of its states and insignificant expanding the products of STG. The problem of replacing an arbitrary synchronous FSM network for the self-checking one with low overhead is discussed.

Detection of false paths in logical circuits by joint analysis of the AND/OR trees and SSBDD-graphs

Consideration was given to the problem of time verification of the combinational circuits, namely, to the problem of determining the false paths. The delays arising in the false paths do not manifest themselves in the circuit operational mode. At determination of the maximal circuit delay as a whole it is recommendable to detect and disregard such paths. It was proposed to reduce the problem of detecting a false path to the search of a test pattern for the stuck-at 0.1 faults of the character of the equivalent normal form corresponding to this path. Search of the test patterns comes to analyzing the conjunctions of the equivalent normal form represented compactly by the AND-OR trees and the structurally synthesized binary decision diagrams. The joint analysis of the AND-OR trees and such diagrams was oriented to reducing the computer burden at seeking the test patterns.

Self-Testing Automaton Networks: Their Design in Programmable Logical Matrices

The design of self-testing synchronous automaton networks in a base of programmable logical matrices is studied. Self-testability of the network component is ensured by encoding the automaton internal states by equilibrium codes and elongating the input state codes. Therefore, the microprogram description of the operation of the component is transformed into a positive monotonic system of disjunctive normal forms, i.e., design specification for the component. Precisely monotonic disjunctive normal forms ensure the monotonic generation of solitary constant faults in programmable logical matrices and input poles of the automaton component at the component outputs and steady propagation of the aftereffects of a faults from its emergence point in some component up to the network outputs. Therefore, testers can be used only for external components, whose outputs are the network outputs, and only the output of these components can be observed without regard for their internal states.

Minimizing the Boolean function system oriented toward self-checking finite-state machine design

Minimization of a partially monotone function system describing the finite-state machine (FSM) behavior is considered. A notion of a prime system implicant with maximal characteristics is introduced. It is proved that the shortest irredundant sum of the implicants is a union of the shortest irredundant sums of implicants with the same characteristics. In all implicants, the literals corresponding to the state variables have no inversions. The shortest irredundant sum of the implicants is used for FSM self-checking design.

Properties of pairs of test vectors detecting path delay faults in high performance VLSI logical circuits

A single path delay fault of a circuit is reduced to a fault in the literal in the equivalent normal form (ENF) that corresponds to the path that acts during the path delay. Based on the analysis of the ENF circuit, we have found properties of pairs of robust and nonrobust test vectors. We show possibilities to reduce the length of the test for path delay faults.