Ekaterina Nikolaeva

Test Generation for Single and Multiple Stuck-at Faults of a Combinational Circuit Designed by Covering Shared ROBDD with CLBs

A combinational circuit is derived with covering the proper Shared ROBDD by CLBs in the frame of FPGA technology. Single stuck-at faults at the CLBs poles and multiple faults constituted from such single stuck-at faults are considered. It is shown that the test pattern as for single stuck-at fault so for multiple fault there always exists. The test pattern for a multiple fault is the special test pattern for the special single stuck-at fault forming the multiple one. Test for all multiple faults is derived from any test for all single stuck-at faults. The length of the multiple faults test is linear function of the single faults test length. A multiple fault test is the one of high quality. In particular SEU and bridge faults may manifest themselves as multiple faults at the CLBs poles. Deriving test for all multiple faults was executed for the certain bench-marks. For them the length of the multiple faults test is about the twice length of the single faults test.

PDF testability of the circuits derived by special covering ROBDDs with gates

Circuits obtained by covering ROBDD nodes with special gate subcircuits are considered. Formulae derived from their structural descriptions are investigated. Based on the results of investigations algorithms of deriving test pairs for robust testable PDFs and validatable non robust testable PDFs of such circuits are developed. Possibilities of cutting calculations under finding the longest circuit paths are discussed.

PDFs testing of combinational circuits based on covering ROBDDs

A method of deriving test pair v1, v2 for robust PDFs of special combinational circuit is suggested. Circuit is obtained by covering Shared ROBDD with LUT based CLBs. Test for all PDFs of a circuit is test for all multiple PDFs and for single stuck-at faults at the CLB poles of a circuit.

A fault-tolerant sequential circuit design for SAFs and PDFs soft errors

This paper presents a fault-tolerant synchronous sequential circuit design based on self-checking system with low overhead. The scheme has a self-checking sequential circuit, a not self-testing checker and a normal (unprotected) sequential circuit. It is proved the reliability properties of the suggested scheme both for single stuck-at faults at gate poles and path delay faults transient and intermittent.

Combinational circuits without false paths

It is known that identifying false paths allows improving a circuit performance but finding false paths is associated with large calculations. In this paper we suggest methods of combinational circuit design that guarantee an absence of false paths in the resulting circuits. Some design methods keeping the specification formulae are considered. The sufficient condition of an absence of false paths in a combinational circuit is formulated. It is shown that the certain types of specification formulae together with the proper design methods keeping the formulae provide this condition for resulted circuits. Examples of the circuits without false paths are given.