Sergey Ostanin

Self-checking Synchronous FSM Network Design with Low Overhead

A method of a self-checking synchronous Finite State Machine (FSM) network design with low overhead is developed. Checkers are used only for FSMs, which output lines are at the same time output lines of the network. The checkers observe output lines of these FSMs. The method is based on reducing the problem to a self-checking synchronous FSM design. The latter is provided by applying a special description of FSM namely, so-called unate Programmable Logic Array (PLAu) description. Single stuck-at fault on the FSM poles and gate poles are considered. PLA realization ofFSM allows a factorized or multilevel logic synthesis. They both provide a unidirectional manifestation of the above mentioned faults on the output lines of the corresponding FSMs. This realization also gives rise to a transparency of each component FSM of the network for the faults. PLA realization is derived from the State Transition Graph (STG) description of FSMs with using the m-out-of-n encoding of its states and insignificant expanding the products of STG. The problem of replacing an arbitrary synchronous FSM network for the self-checking one with low overhead is discussed.

Survivable self-checking sequential circuits

This paper presents a method for designing totally self-checking synchronous sequential circuits (SSC), and investigates their behavior in presence of transient faults. We deal with the case when the circuit is able to recover after the number of clocks. We call SSC owing this property as a survivable SSC. A concept of a partially monotonous SSC is developed in the paper. It is proven that the partially monotonous SSCs are survivable.

Test Generation for Single and Multiple Stuck-at Faults of a Combinational Circuit Designed by Covering Shared ROBDD with CLBs

A combinational circuit is derived with covering the proper Shared ROBDD by CLBs in the frame of FPGA technology. Single stuck-at faults at the CLBs poles and multiple faults constituted from such single stuck-at faults are considered. It is shown that the test pattern as for single stuck-at fault so for multiple fault there always exists. The test pattern for a multiple fault is the special test pattern for the special single stuck-at fault forming the multiple one. Test for all multiple faults is derived from any test for all single stuck-at faults. The length of the multiple faults test is linear function of the single faults test length. A multiple fault test is the one of high quality. In particular SEU and bridge faults may manifest themselves as multiple faults at the CLBs poles. Deriving test for all multiple faults was executed for the certain bench-marks. For them the length of the multiple faults test is about the twice length of the single faults test.

Generating all test patterns for stuck-at faults at a gate pole and their connection with the incompletely specified Boolean function of the corresponding subcircuit

The algorithm of generating all test patterns for a stuck-at fault at a gate pole of single-output combinational circuit is suggested. It is based on the method of redefining products suggested before. It is known that a behavior of a subcircuit of a combinational circuit is presented by the incompletely specified Boolean function. It means that there are the input Boolean vectors of a circuit on which the value of the subcircuit output has no effect on the value of the circuit output. It is set up that the on-set vectors of a subcircuit incompletely specified Boolean function are represented by all test patterns for the stuck-at 0 fault at a subcircuit output and the off-set vectors are represented by all test patterns for the stuck-at 1 fault at the same output. This result may be used for structural combinational circuit minimizing and for partially programmable circuit design. The experimental results are presented.

Detection of false paths in logical circuits by joint analysis of the AND/OR trees and SSBDD-graphs

Consideration was given to the problem of time verification of the combinational circuits, namely, to the problem of determining the false paths. The delays arising in the false paths do not manifest themselves in the circuit operational mode. At determination of the maximal circuit delay as a whole it is recommendable to detect and disregard such paths. It was proposed to reduce the problem of detecting a false path to the search of a test pattern for the stuck-at 0.1 faults of the character of the equivalent normal form corresponding to this path. Search of the test patterns comes to analyzing the conjunctions of the equivalent normal form represented compactly by the AND-OR trees and the structurally synthesized binary decision diagrams. The joint analysis of the AND-OR trees and such diagrams was oriented to reducing the computer burden at seeking the test patterns.

Implementation by the special formula of an arbitrary subset of code words of (m, n)-code for designing a self-testing checker

The problem of synthesis of the self-testing checker for arbitrary l code words of (m, n)-code is considered. In particular, the problem of representation of number l by the sum of cardinal numbers of subsets of the code words corresponding to essential subtrees of the tree representing all code words of (m, n)-code is investigated. The properties such essential subtries are described.

A fault-tolerant combinational circuit design

In this paper we have proposed a fault-tolerant scheme based on totally self-checking system with low overhead. The scheme has only one self-checking module and another one is simplex module (combinational circuit). The analysis of the reliability of proposed scheme is given.

Increasing Manufacturing Yield Using Partially Programmable Circuits with CLB Implementation of Incompletely Specified Boolean Function of the Corresponding Sub-Circuit

The new approach to partially programmable circuit design that allows masking arbitrary gate faults of a logical circuit is considered. It is supposed that only one gate may be fault. There are reserved Configurable Logic Blocks (CLBs) based on Look Up Tables (LUTs) that may mask a gate fault. The suggested approach in comparison with the currently in use ones allows masking any gate fault but not the certain stuck at faults at the gate poles.

A fault-tolerant sequential circuit design for SAFs and PDFs soft errors

This paper presents a fault-tolerant synchronous sequential circuit design based on self-checking system with low overhead. The scheme has a self-checking sequential circuit, a not self-testing checker and a normal (unprotected) sequential circuit. It is proved the reliability properties of the suggested scheme both for single stuck-at faults at gate poles and path delay faults transient and intermittent.

Partially programmable circuit design

The new approach to partially programmable circuit design that allows masking arbitrary gate faults of a logical circuit is considered. It is supposed that only one gate may be fault. There are reserved blocks CLBs (configurable logic block) based on LUTs (Look up table) that may mask the gate fault. The suggested approach in comparison with the currently in use ones allows masking any gate fault but not the certain stuck-at faults at the gate poles.