Abdelkrim Zitouni

Network interface sharing for SoCs based NoC

The demand for IP reuse and system level scalability in System-on-Chip designs is growing. Network-on-chip constitutes a viable solution space to emerging SoC design challenges. In this paper, we present a configurable Network Interface(NI) architecture design approach with smaller area and lower power. The small area is achieved by memory resources sharing in the three modes used by the OCP IP or by many IPs connected to the NI. The low power is obtained by the implementation of a mechanism based on two level of gated clock for power saving. Experimental results show that adaptability, FIFO sharing, and gated clock aspects integrated in the proposed NI allow a significant reduction in terms of area and power.

A low power network interface for network on chip

In recent years, as SoC design research is actively conducted, a large number of IPs are included in one system through network on chip. The real effort and time in using NoC is spent in developing network interfaces (NI) for connecting cores to the NoC. The area and power of NIs should be small and its latency must be kept as low as possible. To reduce power dissipation NIs, we suppose to employ many techniques able to hibernate switchings while no communication is avilable. In this papper, we try to reduce the power dissipation of NoC by reducing the network interface power. We present a hardware design of a low power Network interface design. The low power is obtained by the implementation of a mechanism based on stoppable clock technique for power saving. The stoppable clock technique allows us to shut down each sub module when it is not under running. Experimental results show that adaptability and stoppable clock technique aspects integrated in the proposed NI allow a significant reduction in terms of power while increasing the area.

Design and implementation of low latency network interface for network on chip

The implementation of a high-performance network-on-chip (NoC) requires an efficient design of the network interface (NI) unit that connects the switched network to the IP cores. In this paper, we present a two novel pipelined NI architecture between IPs and router of NOC. These network interfaces allow system designers to send data from IPs to NOC, and vice versa with low latency. We present how we can apply decoupling between computation and communications to achieve the IP modules and interconnections to be designed independently from each other. To validate this approach, we use AMBA AHB IPs standard at the IP side and use the most three used flow control in NoC. This NI was modeled in VHDL and implemented on Xilinx Virtex5 FPGA board. Experimental results show that the proposed Network Interfaces is feasible and efficient and it is characterized by a good performance criterias in terms of area, power, speed, latency, and Throughput.

Arbiter synthesis approach for SoC multi-processor systems

The increasing complexity of Multi-Processor System on Chip (MPSoC) is requiring communication infrastructures that will efficiently accommodate the communication needs of the integrated computation resources. Exploring the arbitration space is crucial for achieving low latency communication. This paper illustrates an arbiter synthesis approach that allows a high performance MPSoC communication for multi-bus and Network on Chip (NoC) architectures. A cost function has been formulated in order to affect the priority order to each component or each set of components in a manner that minimizes the communication latency and generates a multi-level arbiter. The performance of the proposed approach have been analyzed in a design of an 8x8 ATM switch subsystem and a MPEG4 decoder mapped onto a 2-D mesh NoC. The results demonstrate that the MPSoC arbiter is well suited to provide high priority communication traffic with low latencies by allowing a preemption of lower priority transport. The sum of the mean waiting time at the eight ports of the ATM switch is minimum under the MPSoC arbitration scheme (4.30 cycle per word) while it is 3.00 times larger under the poorer performance arbitration scheme. In the case of the MPEG4 decoder, the average packet latency of the MPSoC is about 480 cycles while it is 640 cycles in the poorer performance arbitration scheme under a 0.4 flits/cycle injection rate.

A Quality of Service Network on Chip based on a new priority arbitration mechanism

Multiprocessor system-on-chip (MP-SoC) platforms are emerging as an important trend for SoC design. Network on Chips (NoC) become the preferred on-chip communication platform for current and future SoC architectures. In this paper, we present the design of a new on chip network with Quality-of Service (QoS) support. The proposed routers use new dynamic arbitration architecture with a priority-based scheduler to differentiate between multiple packets with various QoS requirements. A wormhole input queued 2-D mesh router was created to verify the capability of our router. Various parameterized designs were synthesized to provide a comparative study with other implementations in FPGA technology, with different flit size. Finally, a performance study in terms of average latency and throughput of 4×4 mesh 2-D network was conducted to prove the benefit of using the QoS packets and finding the saturation point.

FeRoNoC: Flexible and extensible Router implementation for diagonal mesh topology

Networks on Chip (NoCs) can improve a set of performances criteria, in complex SoCs, such as scalability, flexibility and adaptability. However, performances of a NoC are closely related to its topology. The diameter and average distance represent an important factor in term of performances and implementation. The proposed diagonal mesh topology is designed to offer a good tradeoff between hardware cost and theoretical quality of service (QoS). It can contain a large number of nodes without changing the maximum diameter which is equal to 2. In this paper, we present a new router architecture called FeRoNoC (Flexible, extensible Router NoC) and its Register Transfer Level (RTL) hardware implementation for the diagonal mesh topology. The architecture of our NoC is based on a flexible and extensible router which consists of a packet switching technique and deterministic routing algorithm. Effectiveness and performances of the proposed topology have been shown using a virtex5 FPGA implementation. A comparative performances study of the proposed NoC architecture with others topology is performed.

System level modeling methodology of NoC design from UML-MARTE to VHDL

The evolution of the semiconductor technology caters for the increase in the System-on-Chip (SoC) complexity. In particular, this complexity appears in the communication infrastructures like the Network-on-Chips (NoCs). However many complex SoCs are becoming increasingly hard to manage. In fact, the design space, which represents all the concepts that need to be explored during the SoC design, is becoming dramatically large and difficult to explore. In addition, the manipulation of SoCs at low levels, like the Register Transfer Level (RTL), is based on manual approaches. This has resulted in the increase of both time-to-market and the development costs. Thus, there is a need for developing some automated high level modeling environments for computer aided design in order to handle the design complexity and meet tight time-to-market requirements. The extension of the UML language called UML profile for MARTE (Modeling and Analysis of Real-Time and Embedded systems) allows the modeling of repetitive structures such as the NoC topologies which are based on specific concepts. This paper presents a new methodology for modeling concepts of NoC-based architectures, especially the modeling of topology of the interconnections with the help of the repetitive structure modeling (RSM) package of MARTE profile. This work deals with the ways of improving the effectiveness of the MARTE standard by clarifying and extending some notations in order to model complex NoC topologies. Our contribution includes a description of how these concepts may be mapped into VHDL. The generated code has been successfully evaluated and validated for several NoC topologies.

A modular router architecture desgin for Network on Chip

Network on Chip is an efficient on-chip communication architecture for SoC architectures. It enables the integration of a large number of computational and storage blocks on a single chip. The router is the basic element of NoC with multiple, connecting to other router and to a local IP core. This router architecture can be used later for building a NoC with standard or arbitrary topology with low latency and high speed and High maximal peak performance. The low latency and high speed is achieved by allowing for each input port a routing function which runs in parallel with Link controler and with distributed arbiters. To evaluate our approach, A wormhole input queued 2-D mesh router was created to verify the capability of our router. Various parameterized designs were synthesized to provide a comparative study with other implementations in FPGA thechnology, with different flit size.

Communication synthesis techniques for multiprocessor systems

This paper presents an interactive communication synthesis approach for multiprocessor systems. The aim of the approach consists in mapping a high level specification into a modular and flexible target architecture. The input specification is composed of a set of finite state machines that communicate via a procedural call mechanism. If we assume that the communication critical part is done through a shared memory, this approach allows us to refine the communication structures (interfaces, controllers) in order to reach an operational model easily mappable onto the target architecture. While the choice of communication protocols influences what the best partition is, the target architecture is extendible in order to minimize the communication cost that can be added by the partitioning. The proposed approach is validated through the design of a communication controller.

Low power architecture of motion estimation and efficient intra prediction based on hardware design for H.264

The coding gains of the H.264/AVC video encoder, come from the improvement of the prediction method for intra and inter prediction in goal to achieve best image quality. However, their enormous computation, high complexity and the dissipated power are the main penalties. The approach proposed in this paper invests and exploits the best hardware solution for intra and inter prediction. Intra prediction is based on nine luma modes by using a 4×4 block for predicted MB (macro-block). Inter prediction is based on a novel low power Hardware Adaptive Motion Estimator (HAME), which is essential for the portable systems that integrate the Full Search (FS), the Gradient Search (GS) and the Four Step Search (FSS) algorithms. Our aim is to achieve an acceptable image quality with the reduction of the computational cost by using hardware accelerator. All modules were designed by using Very High Speed Integrated Circuit (VHSIC) and operate with about 350 MHz clock frequency for inter and intra prediction. The Synopsys environments are used and are based on CMOS 45 nm ASIC technology.