Rached Tourki

Definition and Performance Evaluation of a Robust SVM Based Fall Detection Solution

We propose an automatic approach to detect falls in home environment. A Support Vector Machine based classifier is fed by a set of selected features extracted from human body silhouette tracking. The classifier is followed by filtering operations taking into account the temporal nature of a video. The features are based on height and width of human body bounding box, the users trajectory with her/his orientation, Projection Histograms and moments of order 0, 1 and 2. We study several combinations of usual transformations of the features (Fourier Transform, Wavelet transform, first and second derivatives), and we show experimentally that it is possible to achieve high performance using a single camera.We evaluated the robustness of our method using a realistic dataset. Experiments show that the best tradeoff between classification performance and time processing result is obtained combining the original data with their first derivative. The global error rate is lower than 1%, and the recall, specificity and precision are high (respectively 0.98, 0.996 and 0.942). The resulting system can therefore be used in a real environment. Hence, we also evaluated the robustness of our system regarding location changes. We proposed a realistic and pragmatic protocol which enables performance to be improved by updating the training in the current location, with normal activities records.

Optimized spatio-temporal descriptors for real-time fall detection: comparison of support vector machine and Adaboost-based classification

Abstract. We propose a supervised approach to detect falls in a home environment using an optimized descriptor adapted to real-time tasks. We introduce a realistic dataset of 222 videos, a new metric allowing evaluation of fall detection performance in a video stream, and an automatically optimized set of spatio-temporal descriptors which fed a supervised classifier. We build the initial spatio-temporal descriptor named STHF using several combinations of transformations of geometrical features (height and width of human body bounding box, the user’s trajectory with her/his orientation, projection histograms, and moments of orders 0, 1, and 2). We study the combinations of usual transformations of the features (Fourier transform, wavelet transform, first and second derivatives), and we show experimentally that it is possible to achieve high performance using support vector machine and Adaboost classifiers. Automatic feature selection allows to show that the best tradeoff between classification performance and processing time is obtained by combining the original low-level features with their first derivative. Hence, we evaluate the robustness of the fall detection regarding location changes. We propose a realistic and pragmatic protocol that enables performance to be improved by updating the training in the current location with normal activities records.

Design and implementation of network interface compatible OCP For packet based NOC

The idea of using on chip packet switched networks for Interconnecting a large number of IP cores is very practical for designing complex SoCs since it gives possibility of not only reusing IP cores but also the interconnection infrastructure. However, the real effort and time in using these Networks on Chip (NoC) go in developing interfaces for connecting cores to the on-chip network. Standardization of interfaces for these cores such OCP [1] can speed up the development process.In this paper, we present our work of developing a Network Interface for an on-chip network that support OCP IP standard. We chose a range of IP OCP that need to support basic and precise burst mode extension for design an effective. Any cores IP having this configuration can reuse this network interface. Finnaly we will present a comparative study between two Master Network Adaptator and tow Slave Network Adaptator that use respectively handshake and credit based control flow.

A Reconfigurable Implementation of the New Secure Hash Algorithm

The main applications of the hash functions are met in the fields of communications integrity and signature authentication. Many hash algorithms have been investigated and developed in the last years. This work is related to hash functions FPGA implementation. Field programmable gate arrays (FPGAs) being reconfigurable, flexible and physically secure are a natural choice for implementation of hash functions in a broad range of applications with different area-performance requirements. We propose a configurable secure hash algorithm (SHA) processor for extended signature authentication. This paper investigates different optimizations algorithms of recent techniques that have been proposed in the literature. In our implementation based on Xilinx Virtex FPGAs, the throughput of SHA processor is equal to 1296 Mbit/s. Speed/area results from these processors are analyzed and shown to compare favorably with other FPGA-based implementations. A fastest data throughput is achieved by our optimized algorithm

Verification of SystemC transaction level models using an aspect-oriented and generic approach

Transaction level modeling (TLM) has become an accepted and well supported paradigm that is intended to create hardware designs at high abstraction levels. In this paper, we present a methodology that targets the verification of SystemC transaction level models using runtime monitoring. Aspect-oriented programming (AOP) techniques are exploited to handle the high-level TLM features in an automated and generic way. No modifications are needed in the designs SystemC code. In addition, a wide range of functional and performance assertions is addressed. We demonstrate the usefulness of our approach on a realistic system-on-chip platform based on TLM-2.0 standard compliant models and including Open Core Protocol (OCP) interfaces.

Network interface sharing for SoCs based NoC

The demand for IP reuse and system level scalability in System-on-Chip designs is growing. Network-on-chip constitutes a viable solution space to emerging SoC design challenges. In this paper, we present a configurable Network Interface(NI) architecture design approach with smaller area and lower power. The small area is achieved by memory resources sharing in the three modes used by the OCP IP or by many IPs connected to the NI. The low power is obtained by the implementation of a mechanism based on two level of gated clock for power saving. Experimental results show that adaptability, FIFO sharing, and gated clock aspects integrated in the proposed NI allow a significant reduction in terms of area and power.

A low power network interface for network on chip

In recent years, as SoC design research is actively conducted, a large number of IPs are included in one system through network on chip. The real effort and time in using NoC is spent in developing network interfaces (NI) for connecting cores to the NoC. The area and power of NIs should be small and its latency must be kept as low as possible. To reduce power dissipation NIs, we suppose to employ many techniques able to hibernate switchings while no communication is avilable. In this papper, we try to reduce the power dissipation of NoC by reducing the network interface power. We present a hardware design of a low power Network interface design. The low power is obtained by the implementation of a mechanism based on stoppable clock technique for power saving. The stoppable clock technique allows us to shut down each sub module when it is not under running. Experimental results show that adaptability and stoppable clock technique aspects integrated in the proposed NI allow a significant reduction in terms of power while increasing the area.

Computational analysis of blood flow in the retinal arteries and veins using fundus image

The retina is the only tissue in which blood vessels can be visualized non-invasively in vivo. Thus, the study of the retinal hemodynamic has special interest for both physiological and pathological conditions. The aim of this study has been to develop a detailed computational model for a quantitative analysis of the blood flow in physiologically realistic retinal arterial and venous networks. The geometrical outlines of both retinal artery and vein have been extracted from the retinal image acquired from a healthy young adult by a retinal camera Topcon TRC-50EX. The microvascular diameter effect (i.e., Fahraeus-Lindqvist effect) and the hematocrit have been considered in determining the viscosity of the blood in the retinal vessel segments. The blood moves at a velocity that is 2 times less in the veins (maximum 5.4 cm/s) than the velocity at which it moves in the arteries (maximum 11 cm/s) which are in good agreement with in vivo measurements reported in the literature. The pressure drop has been in the range of 11-14 mmHg between the inlet and outlets for the arterial network, and 13-14 mmHg for the vein network. The developed method can be used as a tool for continuous monitoring of the retinal circulation for clinical assessments as well as experimental studies.

Blood vessels extraction and classification into arteries and veins in retinal images

Many retinal diseases are characterized by changes in retinal vessels. The retina vascular structure consists of two kinds of vessels: arteries and veins. An important symptom for Diabetic Retinopathy DR is irregularly wide veins, leading to an unusually low ratio of the average diameter of arteries to veins (AVR). In this paper, we present an approach to separate arteries and veins based on a segmentation and neural classification method. Blood vessels are segmented using two-dimensional matched filters, which derived from Gaussian functions. We used feature vectors based on vessel profile extraction for each segment. The obtained features will be introduced as the input vector of a Multi-Layer Perceptron (MLP); to classify the vessel into arteries and veins ones. Our approach achieves 95.32% correctly classified vessel pixels classification.

Automated optic disc detection in retinal images by applying region-based active aontour model in a variational level set formulation

An efficient optic disk localization and segmentation are important tasks in an automated retinal image analysis system. General-purpose edge detection algorithms often fail to segment the optic disk due to fuzzy boundaries, inconsistent image contrast or missing edge features. This paper presents a method to automatically locate and boundary detect of the optic disk. The detection procedure comprises two independent methodologies. On one hand, a location methodology obtains a pixel that belongs to the OD using iterative thresholding method followed by Principal Component Analysis techniques (PCA) and, on the other hand, a boundary segmentation methodology estimates the OD boundary by applying region-based active contour model in a variational level set formulation (RSF). The method uses an improved geometric active contour model which can not only solve the boundary leakage problem but also is less sensitive to intensity inhomogeneity The results from the RSF method were compared with conventional optic disk detection using a geometric active contour models (ACM) and later verified with hand-drawn ground truth. Results indicate 89% accuracy for identification and 95.05% average accuracy in localizing the optic disc boundary.