Abhijit Patki

25.4 A 500Mb/s 200pJ/b die-to-die bidirectional link with 24kV surge isolation and 50kV/µs CMR using resonant inductive coupling in 0.18µm CMOS

Chip based digital isolators are being developed for higher speed and higher isolation capabilities [1, 2]. These make use of various coupling mechanisms such as capacitive coupling [3] and transformer coupling [4]. A limitation of these technologies is that they need to maintain a low separation (distance through insulation DTI<30µm) through high quality insulators (oxides, polyamides) in order to achieve data rate and isolation performance [2]. These require expensive special process development and special packaging techniques to meet reinforced isolation recommended by IEC 60747-5-5 and VDE 0884-10. Other high-speed die-to-die communication techniques implemented using millimeter-wave and optical solutions are expensive and not designed for isolation. In this work, an isolation technique is proposed where two standard 180nm CMOS dies placed side by side with DTI of more than 500µm, and co-packaged using regular planar MCM flow with package mold compound being the isolation material, achieve asynchronous bidirectional link with >24kV surge isolation capability and greater than 500Mb/s at 175pJ/b. Channel gain is maximized using resonance. Gain is decoupled from channel bandwidth by resetting the channel state variables. This helps in enhancing data rate well beyond what is implied by the bandwidth.

Low complexity, low latency resampling of asynchronously sampled signals

In Signal processing, activity driven data acquisition is of interest as it offers power savings and data compression when dealing with sparse real world signals. However, such schemes naturally result in asynchronous samples which cannot be handled by traditional signal processing. Hence, there is a need for efficient resampling schemes that convert the asynchronous samples to a synchronous stream. This work proposes two novel low latency non-iterative resampling schemes that allow for pipelined hardware and real-time software implementations. The first scheme caters to low complexity applications and is a modification to the Akima algorithm [1]. The second scheme addresses high performance applications and is based on windowed sinc interpolation. Simulation results are presented to demonstrate the performance. Complexity comparison with existing methods is also provided.