Jawaharlal Tangudu

Quantization noise improvement of Time to Digital converter (TDC) for ADPLL

A number of communication applications are moving to digitally motivated architectures for their radio frequency module. This includes GSM-EDGE, WLAN, Bluetooth, GSM-GPRS, WiMAX. The All Digital PLL(ADPLL) forms the core of this architecture. The objective of the ADPLL is to generate a clean carrier frequency ƒc, based on a input reference frequency ƒref. As part of the phase error measurement of the PLL, a Time to Digital converter(TDC) is used to measure the delay between ƒref clock edge and carrier clocking edge. An inverter chain is used to measure this delay as a integer number of basic inverter delay. This measurement error is termed TDC quantization error and effects the phase noise present in the final carrier. Due to the coarse delay of the basic inverter available, TDC introduces large quantization noise at the output of the PLL. This is too high for systems operating at high carrier frequencies or systems which have a tight phase noise requirement. This paper presents techniques to improve TDC quantization noise.

Spur Mitigation in High-Sensitivity GNSS Receivers

The presence of spurious tones in a Global Navigation Satellite Signal (GNSS) receivers RF and analog front-end signal spectrum leads it to compute receivers position erroneously. Addressing spurs is crucial in modern multiconstellation GNSS receivers as their wide bandwidth and coexistence on a shared chip or board with other radios and processors make them highly susceptible to corruption by dynamically varying spurs. Proposed here is a solution to mitigate a large number of spurs in GNSS receivers using a combination of limited number of frequency-tracked digital hardware filters, fast Fourier transform-based spur detectors, and a firmware algorithm predicting and weeding out potentially corrupt satellite measurements. Laboratory validation results from an experimental GNSS receiver in a CMOS system-on-chip are shown to demonstrate its effectiveness.

An ADSL2 and VDSL2 CPE System-on-Chip with Integrated Voice over IP Capabilities for Residential Gateway Applications

This paper describes an SoC design for ADSL2/VDSL2 CPE residential gateways. The chip enables triple play: data, voice and video over DSL along with bridging/routing capabilities. This 90 nm CMOS technology chip integrates high speed data converters, DSL PHY, 4-VOIP channel voice subsystem, MIPS based broadband controller and a range of networking peripherals.

Principal architectural changes in polar transmitter in DRP design for WLAN

In Digital Radio Processor(DRP) an All-digital Phase Locked Loop(ADPLL) forms the core of the architecture with a digitally controlled oscillator(DCO) being the counterpart of Voltage Controlled Oscillator (VCO) in a conventional PLL design. In addition to this, the RF modulation is also performed digitally by feeding Frequency Control Word(FCW) into the ADPLL. This implies that the DCO should be able to support the frequency range requirements for the modulation technique. DCO modulation range for GSM and Bluetooth systems is few hundreds of KHz. However, in order to support WLAN in both 2.4 GHz (ISM band) and 5–5.9 GHz(UNII) bands the DCO needs to have 1.2 GHz modulation range at 12 GHz frequency. Such a DCO becomes extremely sensitive to supply voltage fluctuations. We propose an algorithm which reduces the modulation range requirement of the DCO and hence its sensitivity to supply voltage. In DRP, the modulated clock output of the ADPLL is used as the sampling clock for the digital logic. For GSM and Bluetooth systems the drift introduced in phase samples by using the modulated clock is negligible. However, for WLAN, merely using the modulated clock for sampling is disastrous as it will introduce intolerable drift in the phase samples when compared to phase samples generated by using a constant uniform clock. We propose a predistortion scheme for frequency control words(FCW) to correct this effect of modulated clock.

Techniques to enhance GNSS signal acquisition and tracking sensitivity

Enhancing GNSS acquisition and tracking sensitivity is critical to improving the GNSS user experience in indoor situations. This paper describes various techniques to enhance GNSS signal acquisition and tracking sensitivity and increasing the robustness and availability of position fixes. Specifically, a technique called Staggered Coherent Integration is proposed which enables up to 1 dB improvement in sensitivity compared to conventional techniques. Also discussed are challenges in tracking the weak signals seen in indoor conditions and techniques to improve sustained tracking under these conditions. Analysis and simulation results are shown to demonstrate the effectiveness of the techniques described.