Abhisek Dixit

Reliability Comparison of Triple-Gate Versus Planar SOI FETs

A comparative study of the reliability issues of triple-gate and planar FETs processed on the same silicon-on-insulator wafer is presented. It is shown that the triple-gate architecture does not alter the behavior of the time-dependent dielectric breakdown (BD) for different gate voltages and temperatures. The apparent higher Weibull slope observed in planar devices with respect to the triple-gate devices is ascribed to the area dependence of the time-to-BD detection. In spite of the different surface orientations, low-frequency noise measurements indicate similar values of the interface trap density for triple-gate and planar FETs

Ab initio Study of Metal Grain Orientation-Dependent Work Function and its Impact on FinFET Variability

A novel method to model the effect of local workfunction variation in high-k metal gate nanoscale transistors is proposed. Impact of variability in metal grain granularity on device performance is studied using ab initio density functional theory calculations and device simulations, which show that different metal grain orientations (GOs) can result in large (≥100 mV) variation in metal gate effective work function. Probabilities of occurrence of each GO and the grain size are used to estimate the work-function variations. Full 3-D device simulations are performed to study the effect of metal grain granularity on FinFET and planar MOSFET behavior. Simulated mismatch trends are shown to be in good agreement with the grain diameters and device geometries.

Impact of Fin Sidewall Taper Angle on Sub-14 nm FinFET Device Performance

Recent advances in FinFET technology include fins with tapered sidewalls in addition to conventional vertical sidewall fins. Our 3-D TCAD simulation results suggest that for low to moderately doped fins, vertical sidewall fins have superior electrical performance. Only at extremely high fin doping concentrations could tapered sidewall fins be electrically beneficial.

Measurement and analysis of source/drain contact resistance inFinFETs

FinFET is a key device architecture for the 22-nm CMOS and beyond technology nodes. If special care is not taken, these devices could suffer from high series resistance due to the narrow width of their source/drain regions. Using the electrical characterization of fabricated devices, we extract and analyze the dominant component of this series resistance, namely the source/drain contact resistance.

Characterization of silicide-silicon interface contact resistivity using 1-D dual transmission line model approximation of modified cross bridge kelvin measurements

Conventional 1D single level transmission line model (TLM) to extract silicide-silicon contact resistivity does not take into account silicide sheet resistance. In this paper, 1D dual level TLM model approximation is used for extraction of the silicide sheet resistance and silicide-silicon contact resistivity. Experiments involving Platinum content increase in Nickel Silicide and pre-silicide Carbon implant in Silicon Germanium (SiGe) PMOS is analyzed using our model.

Measurement and Analysis of Parasitic Capacitance in FinFETs with High-k Dielectrics and Metal-Gate Stack

FinFET is one of the promising device architectures for sub-32nm CMOS technology nodes. These non-planar devices benefit from near bulk-Si processing and improved control of short channels due to quasi gate-all-around operation. Their device operation is well studied and optimized in last half decade by various research groups. In this paper, we help evaluate the circuit potential of FinFETs by experimentally comparing their parasitic capacitance to that of the planar FDSOI MOSFETs. It is shown that n- and p-channel FinFETs achieve as high as 50% and 28% parasitic capacitance reduction compared to the planar FDSOI MOSFETs respectively.