Kota V. R. M. Murali

Effect of Band-to-Band Tunneling on Junctionless Transistors

We evaluate the impact of band-to-band tunneling (BTBT) on the characteristics of n-channel junctionless transistors (JLTs). A JLT that has a heavily doped channel, which is fully depleted in the off state, results in a significant band overlap between the channel and drain regions. This overlap leads to a large BTBT of electrons from the channel to the drain in n-channel JLTs. This BTBT leads to a nonnegligible increase in the off-state leakage current, which needs to be understood and alleviated. In the case of n-channel JLTs, tunneling of electrons from the valence band of the channel to the conduction band of the drain leaves behind holes in the channel, which would raise the channel potential. This triggers a parasitic bipolar junction transistor formed by the source, channel, and drain regions induced in a JLT in the off state. Tunneling current is observed to be a strong function of the silicon body thickness and doping of a JLT. We present guidelines to optimize the device for high on-to-off current ratio. Finally, we compare the off-state leakage of bulk JLTs with that of silicon-on-insulator JLTs.

A Tunnel FET for

We propose a modified structure of tunnel field-effect transistor (TFET), called the sandwich tunnel barrier FET (STBFET). STBFET has a large tunneling cross-sectional area with a tunneling distance of ~2 nm. An orientation-dependent nonlocal band-to-band tunneling (BTBT) model was employed to investigate the device characteristics. The feasibility of the STBFET realization using a complementary metal-oxide-semiconductor-compatible process flow has been shown using advanced process calibration with Monte Carlo implantation. STBFET gives a high ION, exceeding 1 mA/μm at IOFF of 0.1 pA/μm with a subthreshold swing below 40 mV/dec. The device also shows better static and dynamic performances for sub-1-V operations. STBFET shows a very good drain current saturation, which is investigated using an ab initio physics-based BTBT model. Furthermore, the simulated ION improvement is validated through analytical calculations. We have also investigated the physical root cause of the large voltage overshoot of TFET inverters. The previously reported impact of Miller capacitance is shown to be of lower importance; the space-charge buildup and its relaxation at the channel drain junction are shown to be the dominant effect of large voltage overshoot of TFETs. The STBFET are shown to have negligible voltage overshoots compared with conventional TFETs.

V_{DD}

The efficient and successful realization of low-power semiconductor devices demands, among other things, the ability to quantitatively model and minimize myriad leakage phenomena. We report herein a general physical model to quantitatively compute crystallographic-orientation-dependent gate-induced drain leakage (GIDL), and its numerical implementation in a continuum-based device simulator. This simulation model has been successfully compared with relevant experimental data derived from heavily doped vertical diodes and 45-nm silicon-based CMOS devices. Also, the process optimization of next-generation 32-nm low-power devices has been discussed in the context of GIDL.

Scaling Below 0.6 V With a CMOS-Comparable Performance

A variant tunnel field effect transistor structure called the binary tunnel field effect transistor (BTFET) for low voltage and near ideal switching characteristics is proposed. The BTFET relies on a binary tunneling distance (HIGH and LOW) for its operation to achieve a steep sub-threshold swing with a predicted range of 5 mV/dec. The transition of tunneling distance from HIGH to LOW state is a step-function of the gate voltage with the threshold voltage as a transition voltage. BTFET has a high on-current due to the high gate electric field and a large tunneling cross section area. An orientation dependent non-local band-to-band tunneling model was used to analyze the DC characteristics of the device.

Crystallographic-Orientation-Dependent Gate-Induced Drain Leakage in Nanoscale MOSFETs

DC and AC NBTI in deep EOT scaled HKMG p-MOSFETs with different IL (scaled to sub 2Å) are measured by UF-MSM method with 10μs delay. A model with interface trap generation (ΔV_IT-IL) at Si/IL interface, hole trapping (ΔV_HT) in IL bulk and trap generation (ΔV_IT-HK) linked to H passivated Oxygen vacancy (Ov-H) defects in IL/HK interfacial transition layer has been proposed. The existence of Ov defects and their energy levels are verified using DFT simulation. The model can successfully predict V_T shift (ΔV_T) during and after DC stress, dependence on pulse duty cycle (PDC) and frequency (f) for AC stress, and gate insulator process dependence with consistent set of parameters. Impact of EOT scaling on DC and AC NBTI is studied, and end-of-life degradation has been estimated.

A Binary Tunnel Field Effect Transistor with a Steep Sub-threshold Swing and Increased ON Current

In this paper, a detailed 3-D numerical analysis is carried out to study and evaluate CMOS logic device and circuit performance of gate-all-around (GAA) Si nanowire (NW) field-effect transistors (FETs) operating in sub-22-nm CMOS technologies. Employing a coupled drift-diffusion room temperature carrier transport formulation, with 2-D quantum confinement effects, we numerically simulate Si GAA NWFET electrical characteristics. The simulation predictions, on the device performance, short channel effects, and their dependence on NW geometry scaling, are in good agreement with the Si NWFET experimental data reported in literature. Superior electrostatic integrity, OFF-state device performance, lower circuit delays, and faster switching in the Si GAA NWFET-based CMOS circuits are numerically demonstrated in comparison with an Si-on-insulator FinFET. The mixed-mode numerical simulations also predict low supply voltage operations for the Si NWFET-based logic circuits.

A comprehensive DC/AC model for ultra-fast NBTI in deep EOT scaled HKMG p-MOSFETs

With decreasing SiO₂ interfacial-layer (IL) thickness, gate currents in SiO₂/HfO₂ dual-layer gate stacks are observed to undergo drastic changes. For an IL thickness below 3 Å, a transition from hole-current-dominated transport to electron-current-dominated transport is observed near operating bias conditions in p-channel field-effect transistors. A tunneling simulation based on the transfer-matrix approach suggests that the band offsets for the SiO₂ and HfO₂ layers are reduced in the submonolayer IL regime ( <; 3 Å), promoting the transition in the conduction mechanism.

CMOS Logic Device and Circuit Performance of Si Gate All Around Nanowire MOSFET

The ability to understand and model the performance limits of nanowire transistors is the key to the design of next generation devices. Here, we report studies on high-mobility junctionless gate-all-around nanowire field effect transistor with carrier mobility reaching 2000 cm(2)/V·s at room temperature. Temperature-dependent transport measurements reveal activated transport at low temperatures due to surface donors, while at room temperature the transport shows a diffusive behavior. From the conductivity data, the extracted value of sound velocity in InAs nanowires is found to be an order less than the bulk. This low sound velocity is attributed to the extended crystal defects that ubiquitously appear in these nanowires. Analyzing the temperature-dependent mobility data, we identify the key scattering mechanisms limiting the carrier transport in these nanowires. Finally, using these scattering models, we perform drift-diffusion based transport simulations of a nanowire field-effect transistor and compare the device performances with experimental measurements. Our device modeling provides insight into performance limits of InAs nanowire transistors and can be used as a predictive methodology for nanowire-based integrated circuits.

On the Electron and Hole Tunneling in a

Independent Trap Generation (TG) monitors such as DCIV and SILC have been used during NBTI, PBTI (and TDDB) stress in differently processed HKMG devices. TG from DCIV for NBTI is attributed to Si/IL and IL/HK interfaces; TG from DCIV for PBTI to IL/HK interface but at similar energy location as NBTI. TG from DCIV shows similar stress bias (VG,STR), time (tSTR) and temperature (T) dependence for NBTI and PBTI, while TG for PBTI from SILC shows very different dependence as it likely scans TG at different spatial and energetic locations. TG contribution to VT shift (ΔVT) is compared to ΔVT from ultra-fast measurements. A compact model is used to predict overall BTI ΔVT considering uncorrelated contributions from independently measured TG and trapping (TP) in pre-existing and generated bulk traps. Impact of IL scaling on BTI and its underlying subcomponents are studied. Physical origins of different TG and TP processes have been identified using Density Functional Theory (DFT) simulations.

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In this work, using self-consistent tight-binding calculations, for the first time, we show that a direct to indirect band gap transition is possible in an armchair graphene nanoribbon by the application of an external bias along the width of the ribbon, opening up the possibility of new device applications. With the help of the Dirac equation, we qualitatively explain this band gap transition using the asymmetry in the spatial distribution of the perturbation potential produced inside the nanoribbon by the external bias. This is followed by the verification of the band gap trends with a numerical technique using Magnus expansion of matrix exponentials. Finally, we show that the carrier effective masses possess tunable sharp characters in the vicinity of the band gap transition points.