Mohit Bajaj

Effect of Band-to-Band Tunneling on Junctionless Transistors

We evaluate the impact of band-to-band tunneling (BTBT) on the characteristics of n-channel junctionless transistors (JLTs). A JLT that has a heavily doped channel, which is fully depleted in the off state, results in a significant band overlap between the channel and drain regions. This overlap leads to a large BTBT of electrons from the channel to the drain in n-channel JLTs. This BTBT leads to a nonnegligible increase in the off-state leakage current, which needs to be understood and alleviated. In the case of n-channel JLTs, tunneling of electrons from the valence band of the channel to the conduction band of the drain leaves behind holes in the channel, which would raise the channel potential. This triggers a parasitic bipolar junction transistor formed by the source, channel, and drain regions induced in a JLT in the off state. Tunneling current is observed to be a strong function of the silicon body thickness and doping of a JLT. We present guidelines to optimize the device for high on-to-off current ratio. Finally, we compare the off-state leakage of bulk JLTs with that of silicon-on-insulator JLTs.

CMOS Logic Device and Circuit Performance of Si Gate All Around Nanowire MOSFET

In this paper, a detailed 3-D numerical analysis is carried out to study and evaluate CMOS logic device and circuit performance of gate-all-around (GAA) Si nanowire (NW) field-effect transistors (FETs) operating in sub-22-nm CMOS technologies. Employing a coupled drift-diffusion room temperature carrier transport formulation, with 2-D quantum confinement effects, we numerically simulate Si GAA NWFET electrical characteristics. The simulation predictions, on the device performance, short channel effects, and their dependence on NW geometry scaling, are in good agreement with the Si NWFET experimental data reported in literature. Superior electrostatic integrity, OFF-state device performance, lower circuit delays, and faster switching in the Si GAA NWFET-based CMOS circuits are numerically demonstrated in comparison with an Si-on-insulator FinFET. The mixed-mode numerical simulations also predict low supply voltage operations for the Si NWFET-based logic circuits.

Carrier transport in high mobility InAs nanowire junctionless transistors.

The ability to understand and model the performance limits of nanowire transistors is the key to the design of next generation devices. Here, we report studies on high-mobility junctionless gate-all-around nanowire field effect transistor with carrier mobility reaching 2000 cm(2)/V·s at room temperature. Temperature-dependent transport measurements reveal activated transport at low temperatures due to surface donors, while at room temperature the transport shows a diffusive behavior. From the conductivity data, the extracted value of sound velocity in InAs nanowires is found to be an order less than the bulk. This low sound velocity is attributed to the extended crystal defects that ubiquitously appear in these nanowires. Analyzing the temperature-dependent mobility data, we identify the key scattering mechanisms limiting the carrier transport in these nanowires. Finally, using these scattering models, we perform drift-diffusion based transport simulations of a nanowire field-effect transistor and compare the device performances with experimental measurements. Our device modeling provides insight into performance limits of InAs nanowire transistors and can be used as a predictive methodology for nanowire-based integrated circuits.

Ab initio Study of Metal Grain Orientation-Dependent Work Function and its Impact on FinFET Variability

A novel method to model the effect of local workfunction variation in high-k metal gate nanoscale transistors is proposed. Impact of variability in metal grain granularity on device performance is studied using ab initio density functional theory calculations and device simulations, which show that different metal grain orientations (GOs) can result in large (≥100 mV) variation in metal gate effective work function. Probabilities of occurrence of each GO and the grain size are used to estimate the work-function variations. Full 3-D device simulations are performed to study the effect of metal grain granularity on FinFET and planar MOSFET behavior. Simulated mismatch trends are shown to be in good agreement with the grain diameters and device geometries.

Random Dopant Fluctuation Induced Variability in Undoped Channel Si Gate all Around Nanowire n-MOSFET

In this brief, the random dopant fluctuation (RDF)-induced threshold voltage (VT) variability, ON current (ION) variability, and VT mismatch in undoped channel Si gate-all-around (GAA) n-nanowire MOSFETs (n-NWFETs) are studied using coupled 3-D statistical device simulations considering quantum corrected room temperature drift-diffusion transport. The RDFs are introduced in the Si NWFET tetrahedral device grid by a 3-D atomistic MonteCarlo technique. The RDF due to discrete random dopants located in the source (S)/drain (D) extension and channel regions of Si GAA n-NWFET are found to impact the device characteristic variability. The numerical VT mismatch analysis and comparison with the Si n-NWFET total AVT measurement data from the literature reveal that RDF still plays a significant source for device random fluctuations in undoped channel Si GAA n-NWFETs. The numerical VT mismatch study indicates the fact that complete suppression of RDF induced device random variability in undoped channel fully depleted MOS devices is still going to be a challenge, as long as doped S/D regions are employed.

Metal-Gate Granularity-Induced Threshold Voltage Variability and Mismatch in Si Gate-All-Around Nanowire n-MOSFETs

The metal-gate granularity-induced threshold voltage (VT) variability and VT mismatch in Si gate-all-around (GAA) nanowire n-MOSFETs (n-NWFETs) are studied using coupled 3-D statistical device simulations considering quantum corrected room temperature drift-diffusion transport. The impact of metal-gate crystal grain size on linear and saturation mode VT variability are analyzed. The VT mismatch study predicts lower mismatch figure of merit (AVT) in TiN-gated Si GAA n-NWFETs compared with the reported experimental mismatch data for TiN-gated Si FinFETs.

Negative differential conductivity and carrier heating in gate-all-around Si nanowire FETs and its impact on CMOS logic circuits

In this paper, we present a fully-coupled and self-consistent continuum based three-dimensional numerical analysis to understand hot carrier and device self-heating effects for device-circuit co-optimization in Si gate-all-around nanowire FETs. We employ three-moment based energy transport formulations and two-dimensional quantum confinement effects to demonstrate negative differential conductivity in Si nanowire FETs and assess its impact on a CMOS inverter and three-stage ring oscillator. We show that strong two-dimensional quantum confinement yields volume inversion conditions in Si nanowire FETs and surround gate geometry enables better short-channel effect control. We find that hot carrier and self-heating effects can degrade ON-state current in Si nanowire FETs and severely limit the logic circuit performance due to the introduction of higher signal propagation delays.

Coupled optical and electrical analysis for thin-film solar cells with embedded dielectric nanoparticles

Combined optical and electrical simulations were performed for thin-film (silicon) solar cell structures with dielectric (silicon-dioxide) nanoparticles embedded in the active region for efficiency enhancement. The efficiency enhancement due to optimally sized nanoparticles is found to be 22% and 15% in the constant coverage area and constant pitch configurations, respectively; further, the enhancement qualitatively follows the trends expected from optical-only simulations. This, however, assumes a good quality dielectric-semiconductor interface, whereas heavy recombination at this interface is seen to degrade the efficiency significantly—setting an upper limit on the surface recombination velocity up to which embedding nanoparticles is beneficial.

Tunneling-triggered bipolar action in junctionless tunnel field-effect transistor

We analyse a novel hybrid semiconductor field-effect transistor (FET), known as the junctionless tunnel FET (JL-TFET). We show that a parasitic bipolar transistor action, which is highly undesirable in conventional metal/oxide/semiconductor FETs and junctionless transistors, is the mechanism that activates the JL-TFET ON state. It is found that the sub-threshold slope (SS) in the JL-TFET is strongly dependent on the silicon thickness and a sub-60 mV/decade SS is observed for a thin silicon body only. We further study the JL-TFET design parameters as regards the effects of the control gate workfunction, P-gate workfunction, and isolation region on the JL-TFET characteristics.

Effect of Metal Gate Granularity Induced Random Fluctuations on Si Gate-All-Around Nanowire MOSFET 6-T SRAM Cell Stability

In this paper, we present a variability-aware 3-D mixed-mode device simulation study of Si gate-all-around (GAA) nanowire MOSFET (NWFET)-based 6-T static random access memory (SRAM) bit-cell stability and performance considering metal-gate granularity (MGG) induced intrinsic device random fluctuations and quantum corrected room temperature drift-diffusion transport. The impact of MGG contributed intrinsic variability on Si GAA n- and p-NWFETs-based SRAM cell static noise margins (SNM), write and read delay time are statistically analyzed. Our statistical simulations predict acceptable stability for the Si NWFET 6-T SRAM cell with VDD downscaling up to 0.5 V. The simulation estimated mean hold SNM values follow a lowering trend with VDD downscaling, similar to the hold SNM experimental data reported in the literature for Si GAA NWFET-based SRAM arrays. We further show a linear variation in statistical variance of hold SNM with gate metal grain size and work function.