Abhishek Patnaik
Missouri University of Science and Technology
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Publication
Featured researches published by Abhishek Patnaik.
international symposium on electromagnetic compatibility | 2017
Abhishek Patnaik; Mihir Suchak; Ramu Seva; Keerthana Pamidimukkala; David Pommerenke; Greg Edgington; Richard Moseley; J. Feddeler; Michael Stockinger; Daryl G. Beetner
Testing and debugging of electrostatic discharge (ESD) or electrical fast transient (EFT) issues in modern electronic systems can be challenging. The following paper describes the design of an on-chip circuit which detects and stores the occurrence of a fast transient stress event at the ESD protection structures in an I/O pad. Measurements and simulations of a test circuit in 90 nm technology show it can accurately detect and record the presence of a transient stress event with a peak current as low as 0.9 A or duration as short as 1 ns and that the detector works well across typical temperature and process variations. The small size of the detector will allow it to be used effectively even in low-cost commercial ICs.
international symposium on electromagnetic compatibility | 2014
Abhishek Patnaik; Yaojiang Zhang; Soumya De; David Pommerenke; Chen Wang; Charles Jackson
In a high-speed connector system, coupling to an adjacent cable-connector system is not uncommon. It is essential to understand and quantify this coupling path in order to mitigate the coupling. Though simulation based methods are widely used, such an approach is generally very time consuming and computationally resource hungry. A measurement based method for quantifying the EMI coupling path between a highspeed connector and an adjacent connector on the same board is presented. This is based on measured S-parameters for the mode conversion representing the coupling from the differential mode in one connector to the antenna mode current on the other connector-cable system. The method is validated on two test structures comparing estimated and measured radiated field emissions.
electrical overstress electrostatic discharge symposium | 2017
Abhishek Patnaik; Mihir Suchak; Ramu Seva; Keerthana Pamidimukkala; Greg Edgington; Richard Moseley; James Feddeler; Michael Stockinger; Daryl G. Beetner
On-die circuits were developed to measure the size of transient electrical events experienced at I/O pads. The circuits allow an integrated circuit (IC) to determine the peak voltages across the electrostatic discharge diodes during the event. Experiments and simulations with a 90 nm test chip show the sensor can determine the peak magnitude of the transient event within 1 A for events larger than 0.7 A and duration longer than 1 ns.
IEEE Transactions on Electromagnetic Compatibility | 2015
Xu Gao; Chunchun Sui; Sameer Hemmady; Joey Rivera; Susumujoe Yakura; David Pommerenke; Abhishek Patnaik; Daryl G. Beetner
Soft errors can occur in digital integrated circuits (ICs) as a result of an electromagnetic disturbance, such as might result from an electrical fast transient (EFT). Many soft errors come from changes in propagation delays through digital logic, which are caused by changes in the on-die power supply voltage. An analytical model was developed to predict timing variations in digital logic as a result of variations in the power supply voltage. The derivation of the analytical delay model is reported. The model was validated experimentally by applying EFTs to a ring oscillator built in a test IC. The predicted and measured ring oscillator frequencies (or periods) agreed within a relative error of less than 2.0%. To further validate the approach, the model was applied to test the response of more complex circuits consisting of NAND/NOR logic gates, binary adders, dynamic logic gates, and transmission gates. The circuits were fabricated on a 0.5 μm test IC and simulated on two additional process technologies (0.18 μm and 45 nm). The model performed well in each case with a maximum relative error of 5.6%, verifying the applicability of the model for analyzing complex logic circuits within a variety of process technologies. The proposed delay model can be used by IC design engineers to predict and understand the change in the propagation delay through logic circuits due to the disturbed power supply.
IEEE Transactions on Electromagnetic Compatibility | 2018
Satyajeet Shinde; Kohei Masuda; Guangyao Shen; Abhishek Patnaik; Tamar Makharashvili; David Pommerenke; Victor Khilkevich
An equivalent two terminal model based on the Thevenin equivalents describes the common mode (CM) currents on the input and output side of two widely used types of dc-to-dc power converters—buck and boost. Thus, it describes a nonlinear circuit by a linear equivalent circuit. The maximized spectrum of the CM currents is extracted for converters with stochastic signals using a novel characterization procedure. The extracted Thevenin model is used in co-simulation combined with a full-wave electromagnetic solver to predict the radiated emissions from the system consisting of the shielded dc–dc converters with attached cables and a DC brushless motor as load. The results using the terminal model agree well with the measurements providing that the actual CM loads are within the range of CM loads used while obtaining the Thevenin equivalent circuit.
international symposium on electromagnetic compatibility | 2017
Abhishek Patnaik; Guangyao Shen; David Pommerenke; Martin Boettcher; Herman Aichele; Christoph Keller; Victor Khilkevich
An electronic system will commonly have multiple emission (or noise) sources, some of which are correlated while others are un-correlated. Measuring the contribution to a node voltage or branch current by an individual source with high accuracy in such a multi source inter-coupled system is a fundamental problem. The problem is further amplified when the signal processing following the measurements is highly sensitive to the error in the measured parameters. This article describes a filtering method which can isolate the measured parameter (voltage or current) of the contribution of other such sources while preserving the phase and magnitude associated with the source under consideration.
electrical overstress electrostatic discharge symposium | 2017
Abhishek Patnaik; Runbing Hua; David Pommerenke
Currents induced on an I/O of a human wearable device IC are predicted using a test IC as a wearable device capable of transient event detection and level sensing. ESD on this pseudo wearable device using the test IC is characterized for different test scenarios and compared to the prediction.
international symposium on electromagnetic compatibility | 2016
Satyajeet Shinde; Abhishek Patnaik; Tamar Makharashvilli; Kohei Masuda; David Pommerenke
An equivalent two terminal model based on Thevenin equivalents describes the common mode currents on the input and output side of a buck converter. A linear equivalent terminal model of the buck converter is created based on measured common mode currents for various common mode loads up to 300 MHz. The results using the terminal model agree well with the measurements for common mode load values that are within the range used for creating the terminal model, however, for loads far away from the characterization load range larger differences occur, as the power converter is a non linear circuit which is modelled by a linear equivalent circuit.
Ashrae Transactions | 2015
Mahdi Moradian; Yunan Han; Abhishek Patnaik; David E. Swenson; David Pommerenke
Ashrae Transactions | 2015
Abhishek Patnaik; Xu Gao; Mahdi Moradian; David E. Swenson; David Pommerenke