Ramu Seva

An on-chip detector of transient stress events

Testing and debugging of electrostatic discharge (ESD) or electrical fast transient (EFT) issues in modern electronic systems can be challenging. The following paper describes the design of an on-chip circuit which detects and stores the occurrence of a fast transient stress event at the ESD protection structures in an I/O pad. Measurements and simulations of a test circuit in 90 nm technology show it can accurately detect and record the presence of a transient stress event with a peak current as low as 0.9 A or duration as short as 1 ns and that the detector works well across typical temperature and process variations. The small size of the detector will allow it to be used effectively even in low-cost commercial ICs.

On-Chip sensors to measure level of transient events

On-die circuits were developed to measure the size of transient electrical events experienced at I/O pads. The circuits allow an integrated circuit (IC) to determine the peak voltages across the electrostatic discharge diodes during the event. Experiments and simulations with a 90 nm test chip show the sensor can determine the peak magnitude of the transient event within 1 A for events larger than 0.7 A and duration longer than 1 ns.

Multi-stage BCH decoder to mitigate hotspot-induced bit error variation

3D heterogeneous integration (commonly termed as 3DIC) of CPU, GPU and DRAM dies vertically interconnected by a massive number of TSVs (Through-Silicon Vias) is expected to overcome limited bandwidth, high latency and energy consumption of off-chip DRAM. However, spatial and temporal variability in temperature (i.e., hotspots) is anticipated to result in bit error variation in DRAM die. A novel multi-stage BCH decoder has been proposed to efficiently address this issue in this work. The proposed multi-stage BCH decoder is designed to tolerate upto a certain maximum number of error bits per codeword, which is estimated from the on-line thermal gradient data, to minimize the decoding latency.

Approximate stochastic computing (ASC) for image processing applications

SC (stochastic computation) has been found to be very advantageous in image processing applications because of its lower area consumption and low-power operation. However, one of the major issues with the SC is its long run-time requirement for accurate results. In this paper, a new technique called the approximate stochastic computing (ASC) approach called the approximate stochastic computing (ASC) focusing on image processing applications is proposed to reduce the computation time of a SC by a factor of 16 at a trade-off of an error percentage of 3.13% in the absolute stochastic value ([0,1)) computed. The proposed technique considers only the first four MSBs of the image pixel value for SC, which introduce a maximum error of 6.25% in the stochastic output. Attempts have been made to reduce this error to 3.13% by linearly increasing the clock cycles from 16 to 17 rather than exponentially (ex: 32, 64,128,256...). Experimental results from SC edge detection circuit indicate that this technique is a promising approach for efficient approximate image processing.

Hybrid GDI-NCL for area/power reduction

Null Convection Logic is a well-known paradigm for designing asynchronous logic circuits. The conventional CMOS-based NCL designs suffers larger area overhead and power consumption. A low power design technique called Gate Diffusion Input (GDI) has been adopted to overcome this limitation. In GDI technology, voltage swing exhibits significant voltage drop across the circuit. Therefore, not suitable for designing large combinational circuits. A novel HYBRID (CMOS+GDI) design is proposed in this work to efficiently address this issue. The HYBRID design utilizes both CMOS and GDI technology to reduce the number of transistor and power dissipation when compared to CMOS NCL circuits. The proposed approach is implemented in NCL Ripple Carry Adder (RCA) and simulated in Cadence Virtuoso for verification.

Parallel decoding for multi-stage BCH decoder

3D heterogeneous processor (commonly termed as 3DHP) integrating multiple processor (such as CPU/GPU) and DRAM dies vertically interconnected by a massive number of Through-Silicon Vias (TSVs) is expected to address the limited bandwidth, high latency and energy consumption of off-chip DRAM. However, spatial and temporal variability due to hotspots in on-chip thermal gradient may result in wide bit error rate variation in DRAM dies. A multi-path BCH decoder has been recently proposed to efficiently address this issue. In this paper, a novel parallel decoding approach for the Multi-Stage BCH decoder is proposed and validated. The proposed approach efficiently leverages the multiple decoding paths to decode multiple words and minimizes the overall decoding latency.