Abinash Roy
University of Illinois at Chicago
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Publication
Featured researches published by Abinash Roy.
design automation conference | 2007
Abinash Roy; Noha H. Mahmoud; Masud H. Chowdhury
With the continuous increase of circuit density, interconnect length, and aspect ratio, the influence of capacitive and inductive coupling on timing characteristics of integrated circuits has become very critical. In this paper, the effects of capacitive and inductive coupling on delay uncertainty and clock skew have been analyzed. Analytical observations and simulation results show that coupling capacitance and mutual inductance have opposite impacts on delay and clock skew variations. It is illustrated that while capacitive coupling worsens both variations, growing inductive coupling can actually counter-balance the negative impacts to some degree.
IEEE Transactions on Very Large Scale Integration Systems | 2010
Abinash Roy; Jingye Xu; Masud H. Chowdhury
This paper presents an in-depth analysis of signal slew and skew variations in coupled inductive lines for different switching patterns. It is revealed that variations of rise/fall time and skew alter the behavior of coupled inductive lines under different switching patterns. We observe that crosstalk noise reduces with increasing signal skew, and the impact of skew variation on crosstalk noise is more prominent for lines with strong capacitive coupling. A performance comparison is done between power supply and ground line as inductive shield, and it is found that ground lines work better than power lines in inductive crosstalk minimization. The 100%-delay measurement technique has been proposed as opposed to the conventional 50%-delay method, and we notice that the 50%-delay technique underestimates the propagation delay for an inductive dominant line with varying signal slew times. Closed-form equations for propagation delay in terms of signal slew time have been derived, which are within 9% of HSPICE-simulated results for a set of interconnect structures. These expressions are simple, and accuracy increases with growing number of interconnect lines.
international conference on microelectronics | 2008
Abinash Roy; Jingye Xu; Masud H. Chowdhury
Continuous effort to achieve higher performance without driving up the power consumption and thermal effects has led the researchers to look for alternative architectures for microprocessors. Like the parallel processing which is extensively used in todays all microprocessors, multi-core architecture which combines several independent microprocessor cores in a single die has currently become very popular in most high performance intergrated circuits. Although multi-core processor offers excellent instruction execution speed with reduced power consumption, optimizing performance of individual processors and then incorporating them by interconnection on a single chip is a non-trivial task. This paper investigates the leading challenges associated with current high performance multi-core processor in terms of interfacing different cores, design automation and verification, software adaptability.
electro information technology | 2007
Abinash Roy; Masud H. Chowdhury
With operating frequencies in GHz regime, problems associated with digital systems in terms of clock skew, jitter, power consumption, bit error rate (BER), and signal integrity are becoming critical in on-chip/off-chip clock distribution networks using conventional copper interconnect technology, which has emerged as a performance limiter for current and future VLSI circuits. In order to mitigate these rising problems and maintain the continuous improvement of high speed integrated circuits, different alternative approaches such as 3-D interconnect, RF/wireless interconnect and optical interconnect have currently been investigated. This paper presents an overview of the limitations of conventional clock distribution networks, and investigates the feasibility and challenges of adopting RF/wireless interconnects in future on-chip and board-level clock distribution networks. Exploratory research results show that these new interconnect technologies will offer desired performances for future high speed clock distribution network operating in multi GHz frequencies if design and integration challenges can be resolved. Based on the survey among the available alternatives, RF/wireless interconnect seems to be the most viable candidate to replace copper interconnect in near future technology nodes (up to 20 GHz).
electro information technology | 2007
Jingye Xu; Abinash Roy; Masud H. Chowdhury
Most of the existing noise analysis techniques in analog integrated circuits apply to only single noise source, and cannot take into account the evolving reality of multiple noise sources interacting with each other. Again the individual and relative impacts of various noise sources will determine what types of remedial steps can be taken. This paper proposes the concept of analyzing the impacts of multiple concurrent noise sources in a circuit network, and applies blind source separation technique (BSS) technique to analyze the characteristics of this compound noise effect in analog integrated circuits. The proposed algorithm extracts the time characteristics of individual noise sources from observed noise at a circuit node. The estimated noise sources can aid in timing and spectral analysis and yield better design techniques.
design, automation, and test in europe | 2007
Jingye Xu; Abinash Roy; Masud H. Chowdhury
This paper addresses the problem of interconnect pipelining from both power consumption and bit error rate (BER) point of view and tries to find the optimal solution for a given wire pipelining scheme in nanometer scale very large scale integration technologies. In this paper a detailed analysis for the dependency of power consumption and BER on the number of flip-flops inserted and repeater size is performed. For the best tradeoff between the wire delay, BER and power consumption, a methodology is developed to optimize the repeater size and the number of flip-flops inserted which maximize a user-specified figure of merit. Then this methodology is applied to calculate the optimal solutions for some International Technology Roadmap for Semiconductor technology nodes.
international symposium on circuits and systems | 2007
Abinash Roy; Masud H. Chowdhury
As technology advances, global interconnects in upper metal layers exhibit significant inductive effect with faster signal rise and fall times. Therefore, existing optimization schemes which optimize various performance parameters of global interconnects, such as, latency, bandwidth, repeater area, and power consumption based on RC delay models are affected by on-chip inductance and leads to degraded chip performance. This paper examines the impacts of inductance on these performance parameters, which were previously based on RC models. This paper also attempts to identify the limitations of these figures of merit (FOMs), and address the impact of line inductance on the methodology of global interconnect width and spacing optimization, and on different figures of merit
international symposium on circuits and systems | 2008
Jingye Xu; Abinash Roy; Masud H. Chowdhury
The design targets of an interconnect are to ensure less delay cycles, high reliability and low power consumption at the same time. This paper presents an in-depth analysis of the dependencies of the reliability (in terms of bit error rate (BER)) and the power consumption of wire pipelining scheme on the number of inserted flip-flops and the size of repeaters. To trade off the design targets, a methodology is developed to optimize the repeater size and the number of flip-flops inserted, which maximizes a user-specified figure of merit. This methodology is demonstrated by calculating the optimal solutions for interconnect pipelining for some International Technology Roadmap for Semiconductor technology nodes.
international symposium on circuits and systems | 2007
Abinash Roy; Noha H. Mahmoud; Masud H. Chowdhury
With aggressive scaling of technology, and corresponding increase of circuit density interconnect has become the most critical factors that influence timing characteristics of integrated circuits performance. This is due to increasing length and aspect ratio of interconnect lines leading to growing capacitive and inductive coupling. In this paper, the effects of capacitive and inductive coupling on delay uncertainty and clock skew have been analyzed. The analysis and the simulation results show that coupling capacitance and mutual inductance have opposite impacts on delay and clock skew variations. It is illustrated that while capacitive coupling worsens both variations, growing inductive coupling can actually counter-balance the negative impacts to some degree.
Vlsi Design | 2007
Jingye Xu; Abinash Roy; Masud H. Chowdhury
In nanometer scale integrated circuits, concurrent insertion of repeaters and sequential elements into the global interconnect lines has been proposed to support multicycle communication--a concept known as interconnect pipelining. The design targets of an interconnect-pipelining scheme are to ensure high reliability, low-power consumption, and less delay cycles. This paper presents an in-depth analysis of the reliability in terms of bit error rate (BER) and the power consumption of wire-pipelining scheme. In this analysis, the dependencies of power consumption and BER on the number of inserted flip-flops, and the size of repeaters are illustrated. To trade off the design targets (wire delay, BER, and power consumption), a methodology is developed to optimize the repeater size and the number of flip-flops inserted which maximize a user-specified figure of merit. The methodology is demonstrated by calculating optimal solutions for interconnect pipelining for some International Technology Roadmap for Semiconductor technology nodes.