Masud H. Chowdhury

Performance analysis of deep sub micron VLSI circuits in the presence of self and mutual inductance

This paper illustrates the growing significance of self and mutual inductances by examining their effects on performance and characteristic issues like propagation delay, rise time, and overshoots. This paper introduces Elmore-like closed form solutions to analyze the behavior of integrated circuits in the presence of self and mutual inductances. The complexity of the expressions introduced here is linear with the number of elements in the interconnect network, and has Elmore delay accuracy characteristics. The propagation delay and overshoots estimated based on these formulae are within 15% of AS/X simulations for a wide range of interconnects from IBMs most recent CMOS technology.

Realizable RLCK circuit crunching

Reduction of an extracted netlist is an important pre-processing step for techniques such as model order reduction in the design and analysis of VLSI circuits. This paper describes a method for realizable reduction of RLCK netlists by node elimination. The method is much faster than model order reduction technique and hence is appropriate as a pre-processing step. The proposed method eliminates nodes with time constants below a user specified time constants. By giving the freedom to the user to select a critical point in the spectrum of nodal time constants, this method provides an option to make a tradeoff between accuracy and reduction. The proposed method preserves the dc characteristics and the first two moments at all nodes. It also recognizes and eliminates all the redundant inductances generated by the extraction tools. The proposed method naturally reduces to TICER according to B. N. Sheehan (1999) in the absence of any inductances.

A New Spatially Rearranged Bundle of Mixed Carbon Nanotubes as VLSI Interconnection

Scaling of device dimensions down to nanometer range helps achieve unprecedented switching speed and multifunctional processing capabilities of nanoelectronic circuits and systems. However, interconnect constraints in the existing and emerging applications are expected to become the primary bottlenecks unless radical change is introduced in the design and technology of on-chip signal communication medium. In response to this demand, various novel and innovative interconnect solutions like carbon nanotube (CNT) are currently being explored as alternatives to metal wires. This paper proposes a unique structure of mixed CNT bundle with a specific arrangement of single-wall and multi-wall CNTs in the bundle. A comprehensive modeling and analysis of the conductance, inductance, and capacitance of the proposed mixed CNT bundle reveals that there will be no significant decrease in the overall conductance of the bundle, but the structural arrangement clearly reduces capacitive crosstalk between neighboring signal lines. Inductive crosstalk is seen to remain unchanged.

Effects of coupling capacitance and inductance on delay uncertainty and clock skew

With the continuous increase of circuit density, interconnect length, and aspect ratio, the influence of capacitive and inductive coupling on timing characteristics of integrated circuits has become very critical. In this paper, the effects of capacitive and inductive coupling on delay uncertainty and clock skew have been analyzed. Analytical observations and simulation results show that coupling capacitance and mutual inductance have opposite impacts on delay and clock skew variations. It is illustrated that while capacitive coupling worsens both variations, growing inductive coupling can actually counter-balance the negative impacts to some degree.

Engineering over-clocking: reliability-performance trade-offs for high-performance register files

Register files are in the critical path of most high-performance processors and their latency is one of the most important factors that limit their size. Our goal is to develop error correction mechanisms at the architecture level. Utilizing this increased robustness, the clock frequencies of the circuits are pushed beyond the point of allowing full voltage swing. This increases the errors observed due to noise and other external factors. The resulting errors are then corrected through the error correction mechanisms. We first develop a realistic model for error probability in register files for a given clock frequency. Then, we present the overall architecture, which allows the error detection computation to be overlapped with other computation in the pipeline. We develop novel techniques that utilize the fact that at a given instance many physical registers are not used in superscalar processors. These underutilized registers are used to store the values of active registers. Our simulation results show that for a fixed architecture the access times to the registers can be reduced by as much as 80% while increasing the number of execution cycles by 0.12%. On the other hand, by reducing the register file access pipeline stages by 75%, the average number of execution cycles of SPEC applications can be reduced by 11.5%.

Innovative power gating for leakage reduction

Leakage has become one of the most dominant factors of power management and signal integrity of nanometer scale integrated circuits. Recently, power gating structures has proven to be effective in controlling leakage. In this paper an alternative dual-F/A reduced power gating structure is proposed for better reduction of leakage currents, especially for low-power, high-performance portable devices. The proposed technique maintains an intermediate power saving state as well as the conventional power cut-off state. The experimental results have demonstrated that the proposed technique can significantly reduce leakage current and associated power consumptions during the HOLD and CUT-OFF power saving modes.

Controlling Ground Bounce Noise in Power Gating Scheme for System-on-a-Chip

Conventional power gating techniques for minimizing leakage currents introduce ground bounce noise during power mode transition. Here an analysis of ground bounce due to power mode transition in power gating structures is presented. An innovative power gating approach is proposed, which in addition to targeting maximum reduction of major leakage currents will provide a way to control ground bounce during power mode transition. The proposed power gating technique will have an additional intermediate HOLD mode along with conventional CUTOFF and RUN modes. Its stepwise turning on feature will provide higher reduction of the magnitude of peak current and voltage glitches in the power distribution network as well as the minimum time required to stabilize power and ground as compared to other similar techniques.

Analysis of the Impacts of Signal Slew and Skew on the Behavior of Coupled RLC Interconnects for Different Switching Patterns

This paper presents an in-depth analysis of signal slew and skew variations in coupled inductive lines for different switching patterns. It is revealed that variations of rise/fall time and skew alter the behavior of coupled inductive lines under different switching patterns. We observe that crosstalk noise reduces with increasing signal skew, and the impact of skew variation on crosstalk noise is more prominent for lines with strong capacitive coupling. A performance comparison is done between power supply and ground line as inductive shield, and it is found that ground lines work better than power lines in inductive crosstalk minimization. The 100%-delay measurement technique has been proposed as opposed to the conventional 50%-delay method, and we notice that the 50%-delay technique underestimates the propagation delay for an inductive dominant line with varying signal slew times. Closed-form equations for propagation delay in terms of signal slew time have been derived, which are within 9% of HSPICE-simulated results for a set of interconnect structures. These expressions are simple, and accuracy increases with growing number of interconnect lines.

Mixed carbon nanotube bundles for interconnect applications

The increasing resistivity of copper with scaling and demands for higher current density are the driving forces behind the ongoing investigation for new wiring solutions for deep nanometer scale VLSI technologies. Metallic carbon nanotubes (CNTs) are promising candidates that can potentially address the challenges faced by copper, and thereby extend the lifetime of electrical interconnects. This article examines the state of the art in CNT applications with focus on CNT interconnect research. It is observed that individually, single-wall carbon nanotubes (SWCNTs) and multi-wall carbon nanotubes (MWCNTs) exhibit characteristics that can be better exploited when a combination of the two is used – in the form of a CNT bundle that plays a vital role in interconnect applications. The focus here is that the usage of a combination of SWCNT (at the centre area of the bundle) and MWCNT (on the outside) provides great performance boost with lower interaction and crosstalk between neighbouring CNT bundles. Simulation results show that the resistance, capacitance, and inductance of a CNT depend on the probability of metallic CNTs present in the bundle and the length of the nanotube. Because Cu is metallic, it indicates that using a higher number of metallic nanotubes in the bundle would aid the CNT bundle performance. In addition, using MWCNT on the outer periphery of the bundle and SWCNT in the centre of the bundle would be the ideal way to maximise the performance of the bundle. Based on the observations we provide an analysis of why a mixed CNT bundle would be highly suitable as interconnections.

A Hybrid Scheme for On-Chip Voltage Regulation in System-On-a-Chip (SOC)

Conventional off-chip or single-stage on-chip converter will fail to meet the demand for different supply voltage domains for various functional blocks/cores in traditional or future multi-/many-core system-on-a-chips (SOCS). In this paper, a hybrid two-stage voltage regulation scheme is proposed, where the first stage consists of a switching voltage regulator located off-chip, and the second stage consists of a tree structure of linear regulators located on the chip. This approach proves to be efficient, simple and less costly compared to other options that offer total on-chip integration of a switching regulators. The difficulties and limitations of on-chip switching regulator have been analyzed. For the tree structure of on-chip linear regulators two different architectures (cascaded and parallel) have been proposed. It is demonstrated that a cascaded tree of linear regulators is a better solution than a parallel tree structure from performance point of view.