Jingye Xu

Analysis of the Impacts of Signal Slew and Skew on the Behavior of Coupled RLC Interconnects for Different Switching Patterns

This paper presents an in-depth analysis of signal slew and skew variations in coupled inductive lines for different switching patterns. It is revealed that variations of rise/fall time and skew alter the behavior of coupled inductive lines under different switching patterns. We observe that crosstalk noise reduces with increasing signal skew, and the impact of skew variation on crosstalk noise is more prominent for lines with strong capacitive coupling. A performance comparison is done between power supply and ground line as inductive shield, and it is found that ground lines work better than power lines in inductive crosstalk minimization. The 100%-delay measurement technique has been proposed as opposed to the conventional 50%-delay method, and we notice that the 50%-delay technique underestimates the propagation delay for an inductive dominant line with varying signal slew times. Closed-form equations for propagation delay in terms of signal slew time have been derived, which are within 9% of HSPICE-simulated results for a set of interconnect structures. These expressions are simple, and accuracy increases with growing number of interconnect lines.

Multi-core processors: A new way forward and challenges

Continuous effort to achieve higher performance without driving up the power consumption and thermal effects has led the researchers to look for alternative architectures for microprocessors. Like the parallel processing which is extensively used in todays all microprocessors, multi-core architecture which combines several independent microprocessor cores in a single die has currently become very popular in most high performance intergrated circuits. Although multi-core processor offers excellent instruction execution speed with reduced power consumption, optimizing performance of individual processors and then incorporating them by interconnection on a single chip is a non-trivial task. This paper investigates the leading challenges associated with current high performance multi-core processor in terms of interfacing different cores, design automation and verification, software adaptability.

Dual diode-Vth reduced power gating structure for better leakage reduction

Leakage has become one of the most dominant factors of power management and signal integrity of nanometer scale integrated circuits. Recently, power gating structures has proven to be effective in controlling leakage. In this paper an alternative dual diode-Vth reduced power gating structure is proposed for better reduction of leakage currents, especially for low-power, high-performance portable devices. The proposed technique maintains an intermediate power saving state as well as the conventional power cut-off state. Experimental results have demonstrated that the proposed technique can significantly reduce leakage current and associated power consumptions during the HOLD and CUT-OFF power saving modes. It has also been demonstrated that the proposed technique significantly reduces ground bounce due to power mode transition.

Noise separation in analog integrated circuits using blind source separation

Most of the existing noise analysis techniques in analog integrated circuits apply to only single noise source, and cannot take into account the evolving reality of multiple noise sources interacting with each other. Again the individual and relative impacts of various noise sources will determine what types of remedial steps can be taken. This paper proposes the concept of analyzing the impacts of multiple concurrent noise sources in a circuit network, and applies blind source separation technique (BSS) technique to analyze the characteristics of this compound noise effect in analog integrated circuits. The proposed algorithm extracts the time characteristics of individual noise sources from observed noise at a circuit node. The estimated noise sources can aid in timing and spectral analysis and yield better design techniques.

Better leakage reduction by exploiting the built-in MOSFET-Vth characteristics

Leakage has become one of the most dominant factors of power management and signal integrity of nanometer scale integrated circuits. Recently, power gating structures has proven to be effective in controlling leakage. In this paper an alternative dual-Vth reduced power gating structure is proposed for better reduction of leakage currents, especially for low-power, high-performance portable devices. The proposed technique maintains an intermediate power saving state as well as the conventional power cut-off state. Experimental results have demonstrated that the proposed technique can significantly reduce leakage current and associated power consumptions during the hold and cut-off power saving modes. It has also been demonstrated that the proposed technique significantly reduces ground bounce due to power mode transition.

Analysis of Power Consumption and BER of Flip-flop Based Interconnect Pipelining

This paper addresses the problem of interconnect pipelining from both power consumption and bit error rate (BER) point of view and tries to find the optimal solution for a given wire pipelining scheme in nanometer scale very large scale integration technologies. In this paper a detailed analysis for the dependency of power consumption and BER on the number of flip-flops inserted and repeater size is performed. For the best tradeoff between the wire delay, BER and power consumption, a methodology is developed to optimize the repeater size and the number of flip-flops inserted which maximize a user-specified figure of merit. Then this methodology is applied to calculate the optimal solutions for some International Technology Roadmap for Semiconductor technology nodes.

Latch Based Interconnect Pipelining For High Speed Integrated Circuits

Aggressive optimization of global interconnect and various improvement skims, such as, repeater insertion, advancement of interconnect materials and use of low dielectrics constant materials are not sufficient to ensure the required performance of high-performance nanometer-scale integrated circuits, since interconnect delays will far exceed the device delays, and multiple clock cycles may be needed for cross-chip signal communication. Unconventional methodologies like insertion of sequential elements in interconnects lines -a concept that has become known as interconnect pipelining - are required to find acceptable solution beyond traditional buffer-insertion based interconnect systems. Here a survey of the issues and challenges in realizing interconnect pipelining technique are presented. Wire pipelining can be based on two approaches - edge triggered flip-flops based and transparent latch based pipelining. Here a set of analytical models is developed to study the implementation of latch based wire pipelining. The proposed analytical models can be used to predict the minimum number, position and feasible region of latches required for wire pipelining scheme

Fast Waveform Estimation (FWE) for Timing Analysis

This paper proposes a new technique, fast waveform estimation (FWE), to quickly and accurately estimate the output waveform for general resistance-capacitance (RC) interconnect networks in the presence of coupling noise. It is a common view that the traditional transient analysis is not feasible for full-chip timing analysis. The static methods suffer from inaccuracy and inability to capture the non-monotonic nature of signal waveform in the presence of coupling noise. The dynamic methods, such as, general model order reduction techniques provide a good compromise between the accuracy and efficiency. But they make no use of the typical topological structures of the general RC interconnect networks. The proposed FWE technique achieves a better overall performance through topological reduction of the general RC interconnect networks. It is demonstrated that the accuracy of the proposed method is comparable to the general model order reduction-based methods while maintaining an efficiency that is comparable to Elmore delay based analysis.

Optimization technique for flip-flop inserted global interconnect

The design targets of an interconnect are to ensure less delay cycles, high reliability and low power consumption at the same time. This paper presents an in-depth analysis of the dependencies of the reliability (in terms of bit error rate (BER)) and the power consumption of wire pipelining scheme on the number of inserted flip-flops and the size of repeaters. To trade off the design targets, a methodology is developed to optimize the repeater size and the number of flip-flops inserted, which maximizes a user-specified figure of merit. This methodology is demonstrated by calculating the optimal solutions for interconnect pipelining for some International Technology Roadmap for Semiconductor technology nodes.

Power consumption and BER of flip-flop inserted global interconnect

In nanometer scale integrated circuits, concurrent insertion of repeaters and sequential elements into the global interconnect lines has been proposed to support multicycle communication--a concept known as interconnect pipelining. The design targets of an interconnect-pipelining scheme are to ensure high reliability, low-power consumption, and less delay cycles. This paper presents an in-depth analysis of the reliability in terms of bit error rate (BER) and the power consumption of wire-pipelining scheme. In this analysis, the dependencies of power consumption and BER on the number of inserted flip-flops, and the size of repeaters are illustrated. To trade off the design targets (wire delay, BER, and power consumption), a methodology is developed to optimize the repeater size and the number of flip-flops inserted which maximize a user-specified figure of merit. The methodology is demonstrated by calculating optimal solutions for interconnect pipelining for some International Technology Roadmap for Semiconductor technology nodes.