Ad M. G. Peeters
Philips
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Featured researches published by Ad M. G. Peeters.
symposium on asynchronous circuits and systems | 2010
Ad M. G. Peeters; Frank te Beest; Mark de Wit; Willem C. Mallon
This paper presents a new design template and design flow for the implementation of data-driven asynchronous circuits. It relies on the use of edge-triggered flip-flops as the only storage elements, not only for the datapaths, but also for the control circuits; latches and C-elements that are common in many asynchronous circuit design styles are not required. The design template uses a two-phase handshake protocol for inter-component communication. In a pipeline structure, these circuits operate near the speed of Mousetrap circuits, but the required design-flow is simpler. The implementation style —which we refer to as Click elements — has been chosen to resemble synchronous circuits as much as possible. This allows for the use of conventional optimization and timing tools in the design flow and for a cheaper design-for-test implementation. The click templates are well suited for a data-flow driven compilation flow, which avoids much of the control overhead of traditional syntax-directed compilation. The two-phase circuits show a significant improvement in performance and energy efficiency compared to four-phase single-rail circuits.
international test conference | 2002
Frank te Beest; Ad M. G. Peeters; M. Verra; K. van Berkel; Hans G. Kerkhoff
A test method for asynchronous handshake circuits is presented that is based on synchronous full-scan techniques. The method adds a synchronous test mode to the circuit, in which the entire circuit is controlled by external clocks. This enables the use of conventional test generation tools. The method resulted in an operational flow, capable of automatically testing any handshake circuit with test-quality equal to synchronous circuits. Several circuits have been evaluated, demonstrating over 99% stuck-at fault coverage.
Journal of Electronic Testing | 2003
Frank te Beest; Ad M. G. Peeters; Kees van Berkel; Hans G. Kerkhoff
Handshake circuits form a special class of asynchronous circuits that has enabled the industrial exploitation of the asynchronous potential such as low power, low electromagnetic emission, and increased cryptographic security. In this paper we present a test solution for handshake circuits that brings synchronous test-quality to asynchronous circuits. We add a synchronous mode of operation to handshake circuits that allows full controllability and observability during test. This technique is demonstrated on some industrial examples and gives over 99% stuck-at fault coverage, using test-pattern generators developed for synchronous circuits. The paper describes how such a full-scan mode can be achieved, including an approach to minimize the number of dummy latches in case latches are used in the data path of the handshake circuit.
asia and south pacific design automation conference | 2001
Joep L. W. Kessels; Ad M. G. Peeters
Asynchronous CMOS circuits have the potential for very low power consumption, because they only dissipate when and where active. In addition they have favorable EMC properties, since they emit less energy, which in addition is evenly distributed over the spectrum. The Tangram framework supports the design of asynchronous circuits in a high-level programming language. Using this framework we have designed several chips, such as for instance for pagers and smart cards, which are clearly superior to synchronous designs.
power and timing modeling optimization and simulation | 2003
Joep L. W. Kessels; Ad M. G. Peeters; Suk-Jin Kim
We present the design of a first-in first-out buffer that can be used to bridge clock domains in GALS (Globally Asynchronous, Locally Synchronous) systems. Both the input and output side of the buffer have an independently clocked interface. The design of these kind of buffers inherently poses the problems of metastability and synchronization failure. In the proposed design the probability of synchronization failure can be decreased exponentially by increasing the buffer size. Consequently, at system level one can trade off between safety and low latency. The design is based on two well-known ideas: pipeline synchronization and mousetrap buffers. We first combine both ideas and then in several steps improve the design.
CSP'04 Proceedings of the 2004 international conference on Communicating Sequential Processes: the First 25 Years | 2004
Ad M. G. Peeters
Handshake Technology is a clockless design style for digital circuits, targeted at applications where low energy consumption and ease of integration are essential. Communicating Sequential Processes play a role at various levels of representation. The design-entry language has parallel composition operators, communication channels for broadcast and narrowcast, and input and output actions on these channels. The intermediate architecture is based on Handshake Circuits, which is a network of components connected by handshake channels. In the implementation of these components in VLSI, models of communication again play a role. This paper presents how in Handshake Technology the specification and implementation of handshake components is addressed. It is based on a formal definition of handshake protocols, and outlines the obligation for an implementor to establish a relation between handshake events in the implementation and the specification. Examples of two phase, four phase, and spurious-acknowledge implementations of handshake control circuits are discussed.
symposium on asynchronous circuits and systems | 2001
Joep L. W. Kessels; Ad M. G. Peeters; Torsten Kramer; Markus Feuser; Klaus Ully
By presenting the design of an asynchronous bus interface for the 80C51 microcontroller we show that nonchannel communications are needed to come to a modular and efficient solution. We derive the bus design by applying five transformations to an initial design that is completely based on channel communications. In each of the steps we first discuss the problem to be solved. The final design uses both channel and nonchannel communications, the latter kind of communications being based on shared variables. In principle, communicating through variables is less safe than communicating through channels. We propose so-called communication sessions to obtain safe communications through variables. Communication sessions are well-defined periods of time during which the access rights with respect to a set of variables are transferred from one activity to another We also show that such sessions can be implemented using conventional channels.
symposium on asynchronous circuits and systems | 2004
Ad M. G. Peeters
There are many incentives to tackle the chaos of asynchronous circuit technology. The holy grail of supreme speed is certainly one of them, but it remains a distant goal. However, todays market suffers from other problems for which asynchronous circuits may provide immediate answers - problems such as energy consumption and the integration of analog and digital circuits. Solutions in these domains may have direct impact on the market in areas such as automotive, wireless connectivity, identification and smart cards. A line of business within the Philips Technology Incubator, handshake solutions brings handshake technology to the semiconductor market. Handshake technology is an extremely disciplined asynchronous design style, supported by a complete tool set for design, simulation, prototyping and testing. It enables the industrialization of asynchronous design and has been used in dozens of different IC types with tens of millions of ICs already sold with handshake technology inside. Summary form only given.
Microprocessors and Microsystems | 2003
Kees van Berkel; Ad M. G. Peeters; Frank te Beest
A synchronous mode as well as a scan mode of operation are added to a large class of asynchronous circuits, in compliance with LSSD design rules. This enables the application of mainstream tools for design-for-testability and test-pattern generation to asynchronous circuits. The approach is based on a systematic transformation of all single-output sequential gates into synchronous and scannable versions. By exploiting dynamic circuit operation in scan mode, the overhead of this transformation in terms of both circuit cost and circuit delay is kept minimal.
symposium on cloud computing | 2008
Ad M. G. Peeters; M. de Wit
Asynchronous circuit Design is a disruptive technology that is going through a silent revolution. Once deemed an eternal promise of the future, today, hundreds of millions of asynchronous circuits are produced every year, and many of us may use it on a daily basis without being aware of it. Asynchronous circuits may now be found in the vast majority of electronic (biometric) passports, in in-vehicle networks like CAN and LIN, in MEMS-based sensors such as for measuring tire pressure, in access-control systems, and in near field communication devices such as Nokiapsilas 6131 NFC phone.