Kees van Berkel

The VLSI-programming language Tangram and its translation into handshake circuits

Views VLSI design as a programming activity. VLSI designs are described in the algorithmic programming language Tangram. The paper gives an overview of Tangram, providing sufficient detail to invite the reader to try a small VLSI program himself. Tangram programs can be translated into handshake circuits, networks of elementary components that interact by handshake signaling. The authors have constructed a silicon compiler that automates this translation and converts these handshake circuits into asynchronous circuits and subsequently into VLSI layouts.<<ETX>>

Beware the isochronic fork

Networks of so-called VLSI operators connected by wires form an attractive abstraction of the VLSI medium. However, for the design of non-trivial delay-insensitive circuits so-called isochronic forks are essential. When not carefully implemented, these isochronic forks may give rise to hazardous behavior. Three experiments are used to demonstrate that these forks can be very treacherous by producing hazards in circuits that seem innocent. To avoid such hazards, transition times must be bounded. It is shown that it is also important to limit the variation in logic threshold voltages of VLSI operators. An approach called uniform logic threshold voltages (or “uniform thresholds” for short) is proposed and elaborated on operators. It is also shown that a particular CMOS implementation of sequential operators is not capable of producing uniform thresholds. An alternative implementation is presented for these operators. The idea of uniform thresholds is illustrated by numerous examples.

Vector processing as an enabler for software-defined radio in handheld devices

A major challenge of software-defined radio (SDR) is to realize many giga operations per second of flexible baseband processing within a power budget of only a few hundred mW. A heterogeneous hardware architecture with the programmable vector processor EVP as key component can support WLAN, UMTS, and other standards. A detailed rationale for the EVP architecture, based on the analysis of a number of key algorithms, as well as implementation and benchmarking results are described.

VLSI Programming of Asynchronous Circuits for Low Power

In this chapter we analyze the potential of asynchronous circuits for low power consumption. We set out by reviewing the mechanisms of energy dissipation of digital CMOS ICs in general and clocked circuits in particular. For many applications the generation and distribution of the clock signal account for more than half the power dissipation, directly or indirectly. Much of this wasted clock power — and often much more — can be saved by applying asynchronous circuit techniques.

Synchronous Full-Scan for Asynchronous Handshake Circuits

Handshake circuits form a special class of asynchronous circuits that has enabled the industrial exploitation of the asynchronous potential such as low power, low electromagnetic emission, and increased cryptographic security. In this paper we present a test solution for handshake circuits that brings synchronous test-quality to asynchronous circuits. We add a synchronous mode of operation to handshake circuits that allows full controllability and observability during test. This technique is demonstrated on some industrial examples and gives over 99% stuck-at fault coverage, using test-pattern generators developed for synchronous circuits. The paper describes how such a full-scan mode can be achieved, including an approach to minimize the number of dummy latches in case latches are used in the data path of the handshake circuit.

Adding synchronous and LSSD modes to asynchronous circuits

A synchronous mode as well as a scan mode of operation are added to a large class of asynchronous circuits, in compliance with LSSD design rules. This enables the application of mainstream tools for design-for-testability and test-pattern generation to asynchronous circuits. The approach is based on a systematic transformation of all single-output sequential gates into synchronous and scannable versions. By exploiting dynamic circuit operation in scan mode, the overhead of this transformation in terms of both circuit cost and circuit delay is kept minimal.