Joep L. W. Kessels
Philips
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Featured researches published by Joep L. W. Kessels.
european design automation conference | 1991
Kees van Berkel; Joep L. W. Kessels; Marly Roncken; Ronald W. J. J. Saeijs; Frits D. Schalij
Views VLSI design as a programming activity. VLSI designs are described in the algorithmic programming language Tangram. The paper gives an overview of Tangram, providing sufficient detail to invite the reader to try a small VLSI program himself. Tangram programs can be translated into handshake circuits, networks of elementary components that interact by handshake signaling. The authors have constructed a silicon compiler that automates this translation and converts these handshake circuits into asynchronous circuits and subsequently into VLSI layouts.<<ETX>>
IEEE Design & Test of Computers | 1994
K. van Berkel; R. Burgess; Joep L. W. Kessels; Marly Roncken; Frits D. Schalij; A. Peeters
The authors describe a complete low-power digital compact cassette error corrector. Using Tangram, a high-level programming language, they designed two asynchronous circuits that correct errors on DCC specifications.<<ETX>>
Communications of The ACM | 1983
Joep L. W. Kessels
Permission to copy without fee all or part of this material is granted provided that the copies are not made or distributed for direct commercial advantage, the ACM copyright notice and the title of the publication and its date appear, and notice is given that copying is by permission of the Association for Computing Machinery. To copy otherwise, or to republish, requires a fee and/or specific permission.
international symposium on advanced research in asynchronous circuits and systems | 1997
Joep L. W. Kessels; Paul Marston
We have designed asynchronous standby circuits for a pager decoder which dissipate four times less power and are 40% larger in size than synchronous designs. For the total pager unit this means a 37% reduction in power dissipation for nearly no additional area. The decoder chip, which apart from the standby circuits is completely synchronous, has been fabricated and was first-time-right. Two problems had to be solved to incorporate asynchronous subcircuits in a synchronous environment: synchronization and testing. A synchronization scheme is described that allows a free intermixing of asynchronous and synchronous modules and a test strategy is proposed in which the scan test facilities in the synchronous environment are used to test the asynchronous modules. One function is prevalent in the standby circuits, namely counting. In the appendix we present the asynchronous design of a so-called loadable counter whose power consumption does not depend on its size.
Communications of The ACM | 1977
Joep L. W. Kessels
In the monitor concept, as proposed by Brinch Hansen and Hoare, event queues are used for synchronization. This paper describes another synchronizing primitive which is nearly as expressive as the conditional wait, but can be implemented more efficiently. An implementation of this primitive in terms of P and V operations is given together with a correctness proof. Two examples are presented: the readers and writers problem and the problem of information streams sharing a finite buffer pool.
Acta Informatica | 1982
Joep L. W. Kessels
SummaryThe binary arbitration problem (or, the problem of mutual exclusion between two competitors) is the problem of preventing two competitors from simultaneously possessing the same token. A solution to this problem is presented together with a formal correctness proof. The solution is specific in that it combines the absence of common modifiable variables with the absence of auxiliary activities. Hence, its implementation does not require an arbiter on a lower level or a degree of concurrency of more than two. The solution is generalized for any arbitrary number of competitors by applying the binary solution in a binary arbitration tree.
Proceedings Second Working Conference on Asynchronous Design Methodologies | 1995
K. van Berkel; R. Burgess; Joep L. W. Kessels; Adrianus Marinus Gerardus Peeters; Marly Roncken; Frits D. Schalij; R. van de Wiel
We present a fully asynchronous implementation of a DCC Error Detector. The circuit uses 4-phase handshake signaling and single-rail data encoding, and has been realized using standard cells from a generic cell library. The circuit is obtained by fully automatic translation from a high-level (Tangram) description, using handshake circuits as intermediate architecture. In comparison with a previous double-rail implementation the fabricated IC is 40% smaller (core area), three times faster, and consumes only a quarter of the power. Switching between two power supplies is described as a technique to reduce power dissipation even further. A comparative evaluation also includes an improved double-rail implementation and two synchronous circuits.
asia and south pacific design automation conference | 2001
Joep L. W. Kessels; A. Peeters
Asynchronous CMOS circuits have the potential for very low power consumption, because they only dissipate when and where active. In addition they have favorable EMC properties, since they emit less energy, which in addition is evenly distributed over the spectrum. The Tangram framework supports the design of asynchronous circuits in a high-level programming language. Using this framework we have designed several chips, for instance for pagers and smart cards, which are clearly superior to synchronous designs.
european design automation conference | 1992
Joep L. W. Kessels; K. van Berkel; R. Burgess; Marly Roncken; Frits D. Schalij
Using a programming language for VLSI design, called Tangram, they design a fast and simple VLSI circuit for error decoding in the Compact Disc player. The derivation of the design is straightforward and the result is succinctly expressed in less than one page of Tangram text. All design decisions are based merely on algorithmic and architectural considerations. No particular VLSI knowledge is needed and, therefore, the exercise demonstrates that Tangram allows system designers to design VLSI circuits. The exercise also shows that in a VLSI programming language special language constructs are essential to obtain efficient designs.<<ETX>>
international solid-state circuits conference | 1994
K. van Berkel; R. Burgess; Joep L. W. Kessels; A. Peelers; Marly Roncken; Frits D. Schalij
The promise of chip-wide asynchronous operation is its potential for very low power consumption. This potential is demonstrated by an error-corrector based on digital compact cassette (DCC) specifications, dissipating 80% less than its synchronous counterpart. A reduction in power consumption means longer battery lifetime, important in portable products such as cellular radio and personal audio.<<ETX>>