Adam Golda

Temperature influence on power consumption and time delay

Both the energy consumption and the propagation time delay are very critical parameters of contemporary integrated circuits. It is obvious that a circuit should consume energy as small as possible and ought to work with maximum speed and efficiency. However, these parameters are dependent on temperature, which can change with both external (e.g. high surrounding temperature) and internal (e.g. power dissipated in the circuit) conditions. The article presents the temperature influence on energy consumption and propagation time delay of CMOS ASIC circuits at the example of AMI Semiconductor 0.7 /spl mu/ CMOS C07MD technology (former Alcatel MIETEC CMOS 0.7 /spl mu/m-C07MA-C07MD). The gate was tested under the two conditions: controlled by ideal trapezoid pulse signal, and controlled by real output signal that came from previous gate.

Analysis And Design Of Ptat Temperature Sensor In Digital CMOS VLSI Circuits

The paper presents theoretical analyses, simulations and design of a PTAT (proportional to absolute temperature) temperature sensor that is based on the vertical PNP structure and dedicated to CMOS VLSI circuits. Performed considerations take into account specific properties of materials that forms electronic elements. The electrothermal simulations are performed in order to verify the unwanted self-heating effect of the sensor

Predictive Frequency Control For Low Power Digital Systems

The paper presents techniques of dynamic control of digital integrated systems performance considering die temperature. The dynamic clock throttling (DCT) and the dynamic frequency scaling (DFS) are taken into account. Allowing for the power-time product (pt) a new predictive method that improves the efficiency of DCT and DFS techniques is introduced

Effective Supervisors for Predictive Methods of Dynamic Power Management

The paper presents new supervisors dedicated to predictive methods of dynamic power management, i.e. DCT (dynamic clock throttling), DFS (dynamic frequency scaling), and DVS (dynamic voltage scaling). The presented supervisors make decisions on the basis of current chip temperature; future, current and previous power dissipations. They consist in cooperation with operating system and they are dedicated to high efficiency systems. The proposed supervisors can be implemented in both software and hardware, e.g. as neural network. Not only performance gain but also energy profit can be made in systems that use these supervisors. Simulations results of considered cases show that theoretical improvement of the ideal supervisor is in the range of 7.38 to 16.17% for performance and of 2.47 to 9.88% for energy. The profit of the real supervise method depends on the complexity of supervisor.

Energy losses in digital CMOS integrated circuits: State-of-the-art and future trends

This paper is devoted to investigations into static and dynamic energy consumption of digital CMOS VLSI systems. The analyses are performed for currently available technologies as well as the predictive ones and cover technologies from 32 nm to 3 mum. Next, the formula that describes the ratio of static versus dynamic parts of energy consumption is proposed and further analyses for technology scaling down to 10 nm are carried out.

Optimum control of microprocessor throughput under thermal and energy saving constraints

Abstract The paper presents a method of optimum control of throughput (OCT) of microprocessor (or other processing machine) with taking into account required efficiency, which is taken from operating system, and internal temperature. The optimum performance of integrated system is achieved by means of required efficiency control for safety i.e. low enough temperatures and temperature-based control utilizing thermal feedback for dangerous (high) internal temperatures. The latter control technique, which is obtained using dedicated Temperature-Controlled Oscillator (TCO), assures thermal reliability, i.e. ensures that semiconductor structure temperature do not exceed the critical value of this quantity. The presented method guarantees energy savings and against overheating. The optimum control of throughput of microprocessor is modeled and analyzed using Simulink.

Parameters Identification of Embedded PTAT Temperature Sensors for CMOS Circuits

In this paper, we describe the parameters identification results of PTAT (proportional to absolute temperature) temperature sensors that are implemented in the test chip and dedicated to CMOS integrated circuits. Theirs principles of operation are based on the vertical PNP structure. These sensing elements are uniformly distributed on the chip surface. The chip is dedicated to analyses and verifications of various electro-thermal phenomena in microelectronic VLSI circuits and is fabricated in CMOS 0.7 mum technology. The measurements were performed in a thermal chamber for the temperature range of 288-358 K. The achieved sensitivities of the temperature sensors are within following limits 3.44 to 4.82 mV/K.

Neural Processor as a Dynamic Power Manager for Digital Systems

In this paper the utilization of neural processors as supervisory units that control predictive techniques of dynamic power management is described. Power management becomes more and more important as density of power dissipated in modern integrated circuits, especially microprocessors, continuously raises and can be even higher than 4 megawatts per square meter. It causes temperature increases that might be dangerous for the chip. The presented supervisors that are based on neurons allow correct prediction of chip temperature on the basis of current temperature, power losses that will be consumed in the next units of time, as well as previous power dissipations. Their task is to keep the throughput of high-frequency and high-efficiency systems on the highest possible level under the conditions of energy savings and maintaining safe temperature of chip. The supervisory units are designed using 32-bit and fixed-point precision.

Temperature influence on energy losses in MOSFET capacitors

Abstract The paper deals with the investigation of energy dissipated during processes of charging and discharging of nonlinear MOSFET capacitors. The analysis concerns the CMOS circuits. The effect of simultaneous change of gate-to-source and drain-to-source voltages of one transistor is taken into account. The temperature influence on nonlinear MOSFET capacitors and energy gathered by them is also considered. The theoretical assessment is compared with HSPICE simulation results (BSIM3v3 model) for 0.35 μm technology.

Fractal geometries in lateral flux capacitor design – experimental results

Capacitance density is increased when lateral flux structures are used in CMOS technologies compared to classic parallel-palate capacitors. Lateral-flux capacitors where designed based on three different fractal geometries. Capacitors are designed with and without special MMC metal layer available in some CMOS technologies for capacitor design. For theoretical analysis verification a special ASIC has been designed and fabricated in UMC 0.18um technology. Presented result are obtained by measurement of 5 ICs. Some capacitor structures have much higher capacitance density than classic parallel-plates capacitor without MMC layer. Few presented structures have higher capacitance density than parallel-plate capacitor made with MMC layer. Capacitors have small process parameters spread.