Piotr Kocanda

Environment aware temperature control in processors

This paper presents a new method of controlling processor power throughput based on information on changing cooling conditions. To find out about cooling conditions additional sensor is required. It is mounted on edge of a heatsink. Firstly, a RC thermal model of system IC - heatsink is presented. Parameters for this model were found by using numerical curve fitting to measured heating and cooling curves. PID controllers using Simulink was designed and its practical implementation was compared to classical method of control. New controller achieved higher mean power and lower deviation from target temperature than classical controller.

Improvement of multicores throughput based on environmental conditions

Abstract This article deals with a new, simple and effective method of throughput improvement. The method can be applied in every kind of single and multicore processors. It does not require any integration into integrated circuit topology only modification consists of additional placement of temperature sensor in a heat sink. A simple algorithm controls processors power in such a way that it utilizes full physical ability of integrated circuits working under thermal constraints. Some theoretical investigations are verified by practical experiments.

Quiet passive cooling of high performance microsystems with additional temperature sensor

This paper attempts to investigate the feasibility of chips operating frequency/supply voltage using data about cooling efficiency. It focuses in the introduction of the concept of time shift (TS). TS is the interval of time in which the chip works in higher frequency without any thermal safety violation while its temperature is close to critical thermal threshold (when the cooling efficiency is increasing). The computations of TS values versus different physical conditions of heat sinks were done using RC thermal compact model in Spice environment. Therefore, the authors compare TS values for electronic systems (chip fixed at heat sink) whose heat sinks made of different materials (aluminum and copper) with same geometry. As a result, TS can last till to hundreds of seconds thus it may fulfill a significant part of chip total working time. Based on this assumption, the proposed approach might be a way for increasing the average clock frequency/voltage supply, to improve the die throughput as well as to fully use the thermal ability of a chip fixed to cooling system.

A new idea of effective cooling of integrated circuits

The purpose of this paper is the thermal analysis of the structure consisting of integrated circuit, heat sink, additional temperature sensor and active fan in which the power dissipation is used as the control parameter to get both maximum throughput of a microprocessor and energy saving. It focuses on adjustment of convection coefficient (in other word adjustment of fan rotation speed) at heat sink level with respect to the amount of power dissipated by the chip and environmental circumstances. The duality between electrical and thermal parameters enables to model the RC thermal network of the structure. Therefore, the dynamic thermal behaviour of the integrated system is investigated by utilizing the RC compact model, which is implemented in Spice environment. The simulation result indicates the case of short temperature peak whenever the power dissipation changes. The benefit of this approach is the rapid removal of internal chip energy accumulation due to the adjustment of fan speed. Consequently the cooling systems energy consumption can be minimized, what enhances reliability and efficiency of integrated circuit.

Static and dynamic energy losses vs. temperature in different CMOS technologies

The aim of this paper is energy dissipation analysis in regards to supply voltage and temperature. The basis of all simulations are 12 different transistors coming from 6 different CMOS technologies (from 180nm to 14nm). Dynamic energy used to switch a gate from one state to the other was evaluated in a range of temperature for different supply voltages. In order to guarantee a realistic timing of control signals a special testing circuit was designed. Change of dynamic energy, as a function of temperature, regardless of supply voltage fits in range of -0.5-7.3%. Static power dissipation, a result of existing leakage currents, rises with temperature. When temperature rises from 20 to 100°C static power multiplicities at least 3 times up to 85 times. When operating with low activity static energy consumptions has higher impact on total energy consumption. In most cases one cannot ignore temperature influence on energy consumption.

Design of RISC microcontroller with Dynamic Thermal Management Unit for Temperature-Controlled Oscillator

The paper describes UMC CMOS 0.18 μm (1.8 V) implementation of OctaLynx D microcontroller. The processor is 8-bit RISC structure with built-in Dynamic Thermal Management Unit cooperating with Temperature-Controlled Oscillator. The Dynamic Thermal Management Unit consists of clock source multiplexer, thermal interrupts control unit and special registers containing information of present chip temperature, oscillator frequency control signal and status/control bits. Processor core was written in Verilog hardware description language and designed in top-down technique while memories and analogue parts were designed in full custom technique. The system is dedicated for tests in thermal chamber for development of Dynamic Power Management methods.

A notebook arrangement in aspect of throughput increase

This article presents a simple and effective approach of high performance microprocessors throughput enhancement. It aims at introducing of the notion of Reaction Time (RT). RT is a value that describes the time in which the TΔT control system is fed about the change in ambient cooling condition. Utilization of an additional temperature sensor enables to find out the information about dynamic change of cooling condition. The RT is used for approximating how fast TΔT system can react to the dynamic changes in surrounding environment. Using R-C thermal model in Spice environment, the Reaction Time is analyzed as a variable which is dependent on the convection coefficient and heat generated inside chip. Furthermore, RT values were evaluated versus the placement of additional temperature sensor on the body of a laptop. As results, better location of additional temperature sensor leads a rapid detection of change in surrounding condition in other words short Reaction Time. The advantage of this technique is that the changes of cooling condition can be quickly discovered. Consequently, the control system can react much faster in order to deliver the maximum processors throughput while guarantee the thermal safety.

Optimisation of Ivy Bridge topography

The article presents a quasi-optimum placement of different functional modules in an integrated circuit. The goal of quasi-optimum placement is minimization of maximum chip temperature. Firstly, a RC thermal model of the microprocessor packages is presented. Based on packages geometry and chip lloor topography the HotSpot calculates different parameters for RC thermal model. A New topography of Ivy Bridge processor was modelled using a simple heuristic approach. Therefore, its temperature profile was compared to that obtained through original published floor plan. The crated floor plan provides lower chip maximal temperature than original published one.

Energy losses and DVFS effectiveness vs technology scaling

Purpose – This article aims to present complete analysis of energy losses in complementary metal-oxide semiconductor (CMOS) circuits and the effectiveness of dynamic voltage and frequency scaling (DVFS) as a method of energy conservation in CMOS circuits in variety of technologies. Energy efficiency in CMOS devices is an issue of highest importance with still continuing technology scaling. There are powerful tools for energy conservation in form of dynamic voltage scaling (DVS) and dynamic frequency scaling (DFS). Design/methodology/approach – Using analytical equations and Spice models of various technologies, energy losses are calculated and effectiveness of DVS and DFS is evaluated for every technology. Findings – Test showed that new dedicated technology for low static energy consumption can be as economical as older technologies. The dynamic voltage and frequency scaling are most effective when there is a dominance of dynamic energy losses in circuit. In case when static energy losses are comparable ...

Fractal geometries in lateral flux capacitor design – experimental results

Capacitance density is increased when lateral flux structures are used in CMOS technologies compared to classic parallel-palate capacitors. Lateral-flux capacitors where designed based on three different fractal geometries. Capacitors are designed with and without special MMC metal layer available in some CMOS technologies for capacitor design. For theoretical analysis verification a special ASIC has been designed and fabricated in UMC 0.18um technology. Presented result are obtained by measurement of 5 ICs. Some capacitor structures have much higher capacitance density than classic parallel-plates capacitor without MMC layer. Few presented structures have higher capacitance density than parallel-plate capacitor made with MMC layer. Capacitors have small process parameters spread.