Parag Upadhyaya

A Novel SiGe PIN Diode SPST Switch for Broadband T/R Module

A novel octagonal SiGe p-type intrinsic n-type (PIN) diode single pole single throw (SPST) switch is first implemented in a standard 0.18-mum SiGe BiCMOS technology. Distinctive radio frequency performance of monolithic silicon PIN diode switch is achieved for broadband applications with improvement of its geometry. Over the 2-16GHz frequency band, the PIN diode SPST switch exhibits an insertion loss of less than 1dB and isolation between 42dB to 19dB. An accurate small signal model of series PIN diode is also presented

A new gain controllable on-chip active balun for 5 GHz direct conversion receiver

An on-chip active balun with gain and phase mismatch within 0.5 dB and 1 degree, respectively, integrated with a gain controllability feature, is presented. Applicable for direct conversion receiver circuits, the balun has been designed to operate in the 5-6 GHz range with a bandwidth of 400 MHz. With an output P1dB of -14.4 dBm, it is capable of being used as an independent amplifier in addition to acting as an active balun.

A 5.6-GHz CMOS doubly balanced sub-harmonic mixer for direct conversion -zero IF receiver

A new low power 5.6 GHz doubly balanced sub-harmonic mixer for industrial scientific medical (ISM) band direct conversion - zero IF receiver in 0.25-/spl mu/m CMOS is presented. The mixer uses a power efficient LO frequency generation scheme to overcome the LO self-mixing problems common in conventional direct conversion receivers (DCR). Simulated with 1% gm mismatch, 0.5% load mismatch and 2/spl deg/ LO phase error, the mixer is able to achieve 55 dBm of IIP2, -6.5 dBm of IIP3 and voltage conversion gain of 8 dB while consuming less than 1.75 mA from a single 3 V supply. The mixer also achieves input compression of -12 dBm and an overall double side band noise figure of 5.96 dB. The proposed mixer takes up less than 1 mm/sup 2/ of silicon real estate.

A wide common-mode fully-adaptive multi-standard 12.5Gb/s backplane transceiver in 28nm CMOS

This paper describes the design of a fully-adaptive backplane transceiver embedded in a state-of-the-art, low-leakage, 28nm CMOS FPGA. The receive AFE utilizes a three-stage CTLE to provide selective frequency boost for long-tail ISI cancellation. A 5-tap speculative DFE removes the immediate post-cursor ISI. Both CTLE and DFE are fully adaptive using sign-sign LMS algorithm. A novel clocking technique uses wideband LC and ring oscillators for reliable clocking from 0.6-12.5Gb/s operation. The transmitter utilizes a 3-tap FIR and provides flexibility for supply and ground referenced operation. The transceiver achieves BER <; 10-15 over a 33dB-loss backplane at 12.5Gb/s and over channels with 10G-KR characteristics at 10.3125Gb/s.

Design of high-speed wireline transceivers for backplane communications in 28nm CMOS

This paper describes the design of the architecture and circuit blocks for backplane communication transceivers. A channel study investigates the major challenges in the design of high-speed reconfigurable transceivers. Architectural solutions resolving channel-induced signal distortions are proposed and their effectiveness on various channels is investigated. Subsequently, the paper describes the design of a 0.6-13.1Gb/s fully-adaptive backplane transceiver embedded in state-of-the-art low-leakage 28nm CMOS FPGAs. The receiver front-end utilizes a 3-stage CTLE, a 7-tap speculative DFE, and a 4-tap sliding DFE to remove the immediate post-cursor ISI up to 64 taps. The clocking network provides continuous operation range between 0.6-13.1Gb/s. The transceiver achieves BER <; 10-15 over a 31dB-loss backplane at 13.1Gb/s and over channels with 10GBASE-KR characteristics at 10.3125Gb/s.

A compact 5.6 GHz low noise amplifier with new on-chip gain controllable active balun

A dual gain low noise amplifier for a 5.6 GHz ISM band direct conversion receiver, has been designed using a TSMC 0.25 /spl mu/m CMOS process and features a gain controllable on-chip active balun. The LNA provides gains of 19.5 dB and 12 dB in the two modes with 50% power savings in the low gain mode, while a noise figure of 3.1 dB and an IIP3 of -11.5 dBm have been achieved. A simple and novel gain control technique has been adopted and the gain control circuitry has been integrated with the balun.

A 0.5–16.3 Gb/s Fully Adaptive Flexible-Reach Transceiver for FPGA in 20 nm CMOS

This paper describes a 0.5-16.3 Gb/s fully adaptive wireline transceiver embedded in 20 nm CMOS FPGA. The receiver utilizes bandwidth adjustable CTLE and adjustable output capacitance at the AGC to support wide range of channel loss profiles. A modified 11-tap, 1 bit speculative DFE topology provides reliable operation across all data rates. Low-latency digital CDR ensures high tracking bandwidth while still providing flexibility to support multiple protocols. The transceiver uses ring-oscillator with programmable main and cross-coupled inverter drive-strengths to wide range of operating frequency for low data-rate operation. A wide range low jitter LC-PLL utilizes feedback divider with synchronized CMOS down-counter without a prescaler to achieve a continuous divide ratio of 16-257. The clock distribution uses quadrature-error correction circuit to improve phase interpolator linearity. The transceiver achieves BER <;10-15 over a 28 dB loss backplane at 16.3 Gb/s and over legacy channels with 10 G-KR characteristics at 10.3125 Gb/s. The transceiver meets jitter tolerance specifications for both PCIe Gen3 at 8 Gb/s and PCIe Gen4 at 16 Gb/s in both common-clock and spread-spectrum modes.

2.8 A pulse-position-modulation phase-noise-reduction technique for a 2-to-16GHz injection-locked ring oscillator in 20nm CMOS

High-speed transceivers embedded inside FPGAs require software-programmable clocking circuits to cover a wide range of data rates across different channels [1]. These transceivers use high-frequency PLLs with LC oscillators to satisfy stringent jitter requirements at increasing data rates. However, the large area of these oscillators limits the number of independent LC-based clocking sources and reduces the flexibility offered by the FPGA. A ring-based PLL occupies smaller area but produces higher jitter. With injection-locking (IL) techniques [2-3], ring-based oscillators achieve comparable performance with their LC counterparts [4-5] at frequencies below 10GHz. Moreover, addition of a PLL to an injection-locked VCO (IL-PLL) provides injection-timing calibration and frequency tracking against PVT [3,5]. Nevertheless, applying injection-locking techniques to high-speed ring oscillators in deep submicron CMOS processes, with high flicker-noise corner frequencies at tens of MHz, poses a design challenge for low-jitter operation. Shown in Fig. 2.8.1, injection locking can be modeled as a single-pole feedback system that achieves 20dB/dec of in-band noise shaping against intrinsic VCO phase noise over a wide bandwidth [6]. As a consequence, this technique suppresses the 1/f2 noise of the VCO but not its 1/f3 noise. Note that the conventional IL-PLL is capable of shaping the VCO in-band noise at 40dB/dec [6]; however, its noise shaping is limited by the narrow PLL bandwidth due to significant attenuation of the loop gain by injection locking. To achieve wideband 2nd-order noise shaping in 20nm ring oscillators, we present a circuit technique that applies pulse-position-modulated (PPM) injection through feedback control.

A high IIP2 doubly balanced sub-harmonic mixer in 0.25-/spl mu/m CMOS for 5-GHz ISM band direct conversion receiver

This paper presents a new low power and high IIP2 0.25- /spl mu/m CMOS doubly balanced sub-harmonic mixer for a 5 GHz Industrial Scientific Medical (ISM) band direct conversion-zero IF receiver. Using a 1/2/spl times/LO frequency generation scheme, the sub-harmonic mixer, designed and fabricated, overcomes the LO self-mixing problem common in conventional direct conversion receivers (DCR). Measurements show the sub-harmonic mixer is able to achieve voltage conversion gain of 8.2 dB, input compression, P/sub 1dB/ of -8 dBm and IIP/sub 3/ of -2.5 dBm while consuming only 1.35 mA of DC current. Measured results correlate well with simulated results where with 1% g/sub m/ mismatch, 0.5 % load mismatch and 2/spl deg/ LO phase error, the mixer is able to achieve high IIP/sub 2/ of 55.3 dBm, IIP/sub 3/ of -6.5 dBm, and voltage conversion gain of 8 dB. The proposed mixer takes up less than 1 mm/sup 2/ of silicon real estate, including test die pads.

Design Techniques for Load-Independent Direct Bulk-Coupled Low Power QVCO

Design techniques for a load-independent low-power low-phase-noise CMOS LC direct bulk-coupled quadrature voltage-controlled oscillator (DBC-QVCO) is presented in this paper. A capacitor tapping technique is used to lower the phase noise and achieve load-independent frequency of oscillation. Class-C operation is used to further reduce the phase noise and power consumption. Quadrature coupling is achieved using bulk coupling, leading to reduction in both power and area. The DBC-QVCO has been implemented in a standard 0.18-μm BiCMOS process and occupies an area of 0.3 mm2. The implemented DBC-QVCO achieves a measured phase noise of -114.2 dBc/Hz at 1-MHz offset from the 6.26-GHz carrier while consuming only 3.2 mW from a 1-V power supply. The DBC-QVCO achieves a figure of merit (FOM) of -185.1 dBc/Hz and an FOM with area of -190.3 dBc/Hz, which are among the best compared with recently published QVCOs operating in a similar frequency range.