Aditya P. Karmarkar

Performanace and reliability analysis of 3D-integration structures employing Through Silicon Via (TSV)

Large thermal mismatch stress can be introduced in 3D-Integration structures employing Through-Silicon-Via (TSV). The stress distribution in silicon and interconnect is affected by the via diameter and layout geometry. The TSV induced stress changes silicon mobility and ultimately alters device performance. The mobility and performance change differs in nand p- silicon and is a function of the distance to the TSV. In addition, the TSV induced stress acts on the barrier layer, the landing pad, the interconnects, and the dielectrics. The interactions with defects may lead to crack nucleation and growth, and compromise the structure reliability. Furthermore, the material choice that reduces silicon stress for less impact on performance may increase stresses in other regions where reliability is of concern. This paper studies these effects and their dependence on various integration configurations.

Material, Process and Geometry Effects on Through-Silicon Via Reliability and Isolation

Through-silicon via (TSV) structures with various material and geometry configurations are assessed to study their impact on reliability, isolation and performance. Oxide liner insulators show a larger performance impact as compared to low-k liners and the effect decreases with increasing liner insulator thickness. Higher density of the TSV array causes greater stress impact on carrier mobility and increases the parasitic capacitance. Additionally, low-k liner reduces the parasitic capacitance, but exhibits lower strength and adhesion, therefore degraded reliability. These results provide an important perspective of performance and reliability trade-offs necessary for a robust TSV design.

3D TCAD Modeling For Stress Management In Through Silicon Via (TSV) Stacks

Thermo‐mechanical stresses are introduced in three dimensional integration structures employing TSVs during fabrication process. Stress analysis is required in order to manage the stress related performance and reliability issues in 3D TSV stacks. The TSV parasitic parameters need to be examined at the same time for system design optimization. In this paper, TCAD methodologies for process simulation, stress and parasitic modeling are demonstrated. The mechanical stress impact on the device performance and structural reliability for various materials and geometries is examined. The TSV parasitic parameters and their effects on performance are also analyzed. The correlation between these parameters is determined to achieve the design trade‐offs necessary for optimal 3D integration.

Simulation methodology and flow integration for 3D IC stress management

A new methodology to bridge package and silicon domain simulations is demonstrated using a new data file to facilitate stress information exchange. The flow integration uses equivalent stress conditions to replace sensitive process information and parameterized modules to minimize user interventions for 3D IC stress simulations.

Copper Anisotropy Effects in Three-Dimensional Integrated Circuits Using Through-Silicon Vias

The elastic anisotropy of copper through-silicon vias (TSVs) and its impact on performance and reliability in 3-D integrated structures is examined. Copper TSVs exhibit significant amount of elastic anisotropy, particularly for TSVs with very small diameters. The elastic anisotropy manifests itself in terms of different Youngs moduli in different directions and results in orientation-dependent stress distributions. The copper anisotropy in TSVs is measured, and the impact on stress-induced mobility variation and structural reliability is examined using an advanced technology computer-aided design simulator. It is observed that both the charge carrier mobility and the structural reliability are affected by the anisotropy and its orientation. The copper anisotropy effects studied here become more prominent for TSVs with small diameters and/or large aspect ratios, and need to be assessed thoroughly in order to design robust 3-D structures.

Modeling of interconnect stress evolution during BEOL process and packaging

A novel simulation approach is developed to examine the stress evolution in the chip-to-package interconnect structures during the sequential IC Backend processes followed by packaging / assembly operation. Packaging induced stress in near-bump and BEOL level models is examined using the multi-level FEA methodology. Likewise, the Backend process induced stresses in the interconnect structures is analyzed using a sequential process simulation that looks into stress evolution of the BEOL structure as each metal-dielectric layer is being patterned. Finally, the cumulative impact of packaging induced stress and the BEOL process induced stress on the interconnect structures is examined to demonstrate the significance of this approach in performing a “design dependent” CPI risk analysis for BEOL interconnects.

Analysis of copper plasticity impact in TSV-middle and backside TSV-last fabrication processes

Copper plasticity effects in TSV middle and backside TSV last integration flows are analyzed using an advanced 3D TCAD simulator with model parameters calibrated to match experimental data. In this work, a low thermal budget TSV last integration flow is considered. In contrast to the TSV middle flow, the TSV last flow studied here exhibits insignificant TSV pumping, M1 metal thinning or M1 metal resistance increase. The difference in residual stress profiles in BEOL structure for TSV middle and TSV last processes indicates that the process sequence must be optimized in order to minimize the reliability risks. The mobility change in active silicon for the TSV last process is lower as compared to that for the TSV middle process at room temperature due to the lower temperature excursions during the TSV last integration. This study demonstrates that the TSV integration flow must be designed and selected carefully to meet specific performance and reliability requirements.

Analysis of performance and reliability trade-off in dummy pattern design for 32-nm technology

Deep sub-micron technologies employ dummy metal fills in the interconnect layouts with adequate pre-CMP pattern density distribution to achieve post-CMP planarization. Dummy metal placement has a significant impact on interconnect parasitic capacitance and it also alters the mechanical stresses in the interconnect structure. The combined effects of dummy placement on the parasitic capacitance and the mechanical stresses are examined in this study. The impact of the dummy placement is found to be strongly correlated with the dummy fill pattern. Some patterns studied here result in improved interconnect parasitic parameters but lead to a deterioration in the local stress fields that are of reliability concern. Therefore, the dummy placement must be designed such that both performance and reliability are taken into consideration.

Viscoelastic Modeling and Reliability Assessment of Microelectronics Packages

Viscoelastic stress relaxation occurs at operating temperature in underfill materials of flip-chip packages with high power devices. Multi-level finite element analysis is performed to study the impact of the viscoelastic relaxation on package reliability. The stress simulations reveal that the relaxation in underfill material leads to higher stress concentration in solder bumps. The failure analysis shows that the induced high stress develops higher crack driving forces. The results demonstrate that the underfill material property such as viscosity can shift failure mode from die corner delamination to near bump delamination. Therefore, the numerical study can be used as a guideline to select underfill material for package reliability improvements.

Performance and Reliability Impact of Copper Plasticity in Backside TSV-Last Fabrication Process

The effects of copper permanent deformation during thermal cycles in backside through-silicon via (TSV)-last fabrication process are studied using an advanced 3-D simulator. The plasticity and creep model parameters are chosen to match experimental data. Two sets of different TSV configurations and back end of line (BEOL) layouts are utilized to examine TSV reliability, BEOL reliability, and front-end device performance after postplating thermal excursion. The results indicate that the copper plasticity deformation affects TSV stress distributions for TSV-last fabrication process. The configuration employing a thicker liner made of a softer material shows better TSV and BEOL reliability and lower TSV stress-induced device performance impact. It is also observed that the BEOL layout near the TSV edge needs to be optimized as the BEOL structures in this region experience larger mechanical stress and lower reliability.