Xi-Wei Lin

Stress-Aware Design Methodology

Sub-90 nm CMOS circuits contain a significant amount of mechanical stress in active silicon. This stress is generated by a variety of intentional and unintentional stress sources. Shallow trench isolation is an example of an unintentional stress source, whereas embedded SiGe in the source and drain is an example of an intentional stress source. The amount of stress in each transistor in the circuit depends on the shape of its diffusion area as well as the density of the adjacent layout. The resulting non-uniform stress distribution alters individual transistor performance and, ultimately, the behavior of the circuit. In this paper, several examples are used to illustrate this effect based on design rules for the 45 nm technology node. A number of alternative approaches are suggested for partially suppressing or completely eliminating the stress-induced performance variations

Bringing Manufacturing into Design via Process-Dependent SPICE Models

This paper describes methodology for constructing compact SPICE models as a function of process parameter variations. The methodology involves global extraction of process-dependant SPICE model parameters from silicon calibrated TCAD simulations. The model is validated by comparing device characteristics from the extracted SPICE parameters with those from TCAD simulations. The analysis demonstrates an excellent goodness of fit over the full range of process parameter variations. The process-dependant SPICE models allow direct access to process parameter variations in circuit design. The extracted models are employed in rudimentary digital circuits to investigate the delay variation in response to process deviations. The proposed approach significantly improves design-for-manufacturing (DFM) by allowing for accurate design sensitivity analysis and parametric yield assessment, as a function of statistically independent and measurable process variations

Modeling and optimization of group IV and III–V FinFETs and nano-wires

We described simulation methodologies involving a variety of modeling techniques applied to design and optimization of several key aspects of the 7nm and 5nm transistors and standard library cells. Analysis of channel material engineering for the 7nm FinFETs points to different trade-offs for the HP, SP, and LP leakage specs. Mechanical stability of the fins with high aspect ratio is evaluated as a major factor determining fin shape engineering and transitions from bulk FinFET to SOI FinFET and then to NW. Comparative analysis of the 10 track high 2-input NAND library cells based on different channel materials, different spacer materials, and different transistor architectures suggests that the largest benefits of 3.6x speed gain with 5x reduction in power consumption is achieved by switching from 7nm Si baseline FinFET process to 5nm vertical Si NWs. Within lateral transistors at 7nm design rules, transition from fins to lateral NWs and replacing nitride spacers with oxide spacers offer significant speed/power advantage. The channel material engineering brings the weakest advantage on the library cell level.

Layout Proximity Effects and Modeling Alternatives for IC Designs

Layout-dependent variations significantly affect device modeling, model extraction, and design solutions. A novel approach is proposed in this article to seamlessly integrate physical models of lithography, strained Si, and ion implantation processes, with layout geometry for efficient model generation.

Systematic study of the impact of curved active and poly contours on transistor performance

Rigorous 3D process and device simulation has been applied to transistors with curved channel shapes that are inevitable due to the optical proximity effects. The impact of channel curvature on the transistor performance has been benchmarked using the universal Ion/Ioff coordinates. Systematic study of the different non-rectangular channel shapes included straight lines at an angle different than 90 degrees and concave and convex shapes with different curvature radii. The study reveals that any deviation from the ideal rectangular shape affects transistor performance. The amount of enhancement or degradation depends on particular shape, with on current, threshold voltage, and off current responding very differently to the same shape variation. The type and amount of performance variation is very different for the distorted channel length (i.e. poly gate shape) vs distorted channel width (i.e. active layer shape). Degradation of over 50% in the on current at a fixed off current has been observed in the most unfavorable cases for each of the two critical mask layers. On the other hand, a desirable over 3x off current reduction at a fixed on current can be achieved by selecting a beneficial channel shape.

Comparative Analysis of Semiconductor Device Architectures for 5-nm Node and Beyond

This letter, for the first time, investigates interactive logic cell schemes and transistor architecture scaling options for 5-nm technology node (N5) and beyond. The proposed novel transistors, such as Hexagonal NanoWire (NW) and NanoRing (NR) architectures, are introduced having higher current drivability and lower parasitic capacitance than conventional NW or NanoSlab devices. The standard cell sizing options, including a 1-fin-per-device version and a 2-fin-per-device design, are systematically evaluated. Each device flavor has multiple vertical stacks when wire-like or slab-like structure is used. Comprehensive transistor and logic cell studies demonstrate that the novel NR is the optimal structure for N5 and beyond.

Power-performance-area engineering of 5nm nanowire library cells

We benchmark planar MOSFETs, FinFETs, and nanowires in a wide range of design rules, spanning from 90nm down to 2nm. This benchmarking evaluates inverter switching speed for a load of 70 metal pitches long interconnect wire and a fan-out of one. Planar MOSFET logic slows down sharply at 14nm design rules, mainly due to short-channel effects reducing the driving strength at a fixed off-state leakage level. FinFETs take over at 14nm node and continue providing incremental gains down to 7nm design rules, but slowing down at 5nm due to the dominant parasitic middle-of-line capacitance. Vertical nanowires take over the lead at 5nm design rules and scale gracefully down to at least 5nm node. Based on these results, we perform detailed benchmarking of several design and process options for a 2-input NAND logic cell built on vertical nanowires with 5nm design rules. Benchmarking involves a holistic modeling methodology with 3D advanced carrier transport characterization of the nanowire behavior, 3D extraction of parasitic RC in the library cell, and simulation of power and delay of an 11-stage ring oscillator in HSPICE. Different cell designs and material engineering options offer cell area reduction of 33% with delay and power changing by over 2x.

Charge storage efficiency (CSE) effect in modeling the incremental step pulse programming (ISPP) in charge-trapping 3D NAND flash devices

A CSE (charge storage efficiency) model is proposed to explain the origin of ISPP slope degradation for various charge-trapping NAND Flash devices. Experimentally it is often observed that the programming window is generally degraded as device dimension scales [1], suggesting a strong size effect. Through our model analysis, it is clarified that for a given amount of trapped electron density in the nitride, the programmed Vt shift is gradually reduced with scaled device dimension owing to the increased fringe field effect. The fringe-field effect can be viewed as the increase of effective top-oxide capacitance, leading to the reduced weighting factor of charge storage. We therefore define a CSE value (<;1) to quantitatively account for the fringe field effect that retards the FN programming. Our model suggests that the ISPP slope is equal to CSE. Furthermore, CSE also impacts the stored electron number, retention, and interference. Optimization methods to improve CSE are studied.

Impact of Fabrication Process, Layout Variation and Packaging Process on Cu/Low-k Interconnect Reliability

The industry trend towards smaller feature size and higher integration density leads to multi-level Cu/low-k interconnect schemes with reduced line width and spacing. Mechanical stress is generated during interconnect fabrication. The spatial distribution of the stress is strongly affected by the layout variation. The packaging process generates a global chip level stress that permeates to the local interconnect level. Stress related failures and yield loss are major areas of concern for Cu/low-k interconnects. The effects of fabrication process, layout variation, and packaging process on the final stress distributions in Cu/low-k interconnect structures are examined and the reliability impact of mechanical stress is assessed.

Intentional Distortion of Transistor Shape to Improve Circuit Performance

A mixed-mode 3-D simulation study has been performed for ring oscillators made of 30-nm planar CMOS transistors with nonrectangular channel shapes. Nonrectangular shapes happen unintentionally due to optical proximity effects and can also be introduced intentionally. Transistors with large drains are shown to degrade ring-oscillator performance, whereas transistors with large sources are shown to simultaneously increase the ring-oscillator frequency by 25% and reduce the leakage current by a factor of three.