Adnan Kabbani

Delay analysis of CMOS gates using modified logical effort model

In this paper, modified logical effort (MLE) technique is proposed to provide delay estimation for CMOS gates. The model accounts for the behavior of series-connected MOSFET structure (SCMS), the input transition time, and internodal charges. Also, the model takes into account deep submicron effects, such as mobility degradation and velocity saturation. This model exhibits good accuracy when compared with Spectre simulations based on BSIM3v3 model. Using UMCs 0.13-/spl mu/m and TSMCs 0.18-/spl mu/m technologies, the model has an average error of 4.5% and a maximum error of 15%.

Modeling and Optimization of Switching Power Dissipation in Static CMOS Circuits

This paper introduces a simple and yet accurate closed-form expression to estimate the switching power dissipation of static CMOS gates. The developed model depends on normalizing a gate- switching power to that of the unit standard inverter and it accounts for the effect of internodal capacitances. For different loads, gates and sizes, the developed model shows a good agreement with Spectre simulations using BSIM3v3 model and UMC 0.13 mum technology. The average error introduced by the model is about 2.7%. Moreover, the model has been used to optimize the switching power of a logical path under a specific required time constraint. For the considered scenarios, an average power saving of 20% and power-delay product of 23% are obtained compared to previous techniques.

COMPLEX CMOS GATE COLLAPSING TECHNIQUE AND ITS APPLICATION TO TRANSIENT TIME

In this paper we present a technique to collapse a CMOS gate into an equivalent inverter. This technique considers deep submicron effects such as mobility degradation and velocity saturation as well as operation regions of both the NMOS and PMOS networks of the considered CMOS gate. In addition, the model accounts for the effect of the gates internodal capacitances on the behavior of the equivalent Series Connected MOSFET Structure. Depending on the CMOS inverter transition time model presented in Ref. 1, the developed model has accurately predicted the transition time of different CMOS gates. Considering various loads, input switching, and transistor sizes, the model shows an average error of 6%, including the error introduced by the inverter model, as compared to BSIM3v3 using Spectre.

Library-free synthesis for area-delay minimization

With a limited number of pre-constructed gates available, current standard cell libraries are not well equipped to take full advantage of advances in deep submicron technology by implementing functions as complex gates. As reported, in a technology process capable of supporting five serial MOS devices, 425,803 unique complex gates may be created - clearly much higher than what is currently available in todays cell libraries. A richer cell library allows the technology mapper more freedom to better select matches to reduce area, delay and power consumption. This paper proposes a novel algorithm for mapping an input netlist to a library of virtual cells by minimizing logical effort delay to select a gate architecture which minimizes the design area-delay product. Initial simulation results show an average of 59.95% reduction in transistor count, 44.75% reduction in circuit overall area, 40.06% reduction in area-delay product, at a cost of a 3.4% increase in delay by applying this algorithm to standard benchmark circuits compared to results obtained from synopsys design compiler with high map effort for delay minimization.

Delay macro modeling of CMOS gates using modified logical effort technique

Modified logical effort (MLE) technique is proposed in this paper to provide delay estimation for CMOS gates. The model accounts for the behavior of series connected MOSFET structure (SCMS), the switching input transition time and internodal charges. Also the model takes into account deep submicron effects such as mobility degradation and velocity saturation. This model exhibits a good accuracy when compared with Spectre simulations using BSIM3v3 model. An average error of 3.1% was obtained based on UMCs 0.13/spl mu/m technology.

Technology portable analytical model for DSM CMOS inverter transition time estimation

In this paper, we propose a new analytical model to estimate the transition time of CMOS inverters. Accounting for the main effects of deep sub-micron such as velocity saturation and mobility degradation, the relationship between the input and output transition is discussed and captured by a closed-form expression. The developed model has been formulated to depend only on device model parameters, which are usually provided with the given technology. The proposed model was verified against circuit simulation using Spectre level 11 (BSIM3v3) for a wide range of transistor sizes, output loading and input transition times. It has also been tested for portability between 0.25 /spl mu/m, 0.18 /spl mu/m and 0.13 /spl mu/m technologies Our model showed good accuracy compared to simulation with maximum error of 10% and an average error of 4%.

Logical path delay distribution and transistor sizing

The merits of high performance design are high speed, low power consumption, and small silicon area. Area optimization could be achieved at different levels of the design abstraction. In this paper area-delay optimization technique that depends on library-free synthesis and transistor sizing is presented. This technique can be used to optimize the path delay or to minimize the path area for a specific given required time. It is generated depending on the CMOS inverter delay model, modified logical effort (MLE) model [A. Kabbani, D. Al-Khalili, and A. J. Al-Khalili (2004)] and the CMOS gate transition time model [A. Kabbani (2004)]. The proposed technique achieves better performance as compared to Synopsyss design compiler. For a given required time, the presented technique saves on area-delay product by about 50% on the average.

Technology portable delay model for DSM CMOS inverters

A closed form expression to accurately estimate the delay of a CMOS deep submicron (DSM) inverter is presented in this paper. This model does not depend on any extracted or fitting parameters. Instead it depends on the device model parameters. This model exhibits a good accuracy when compared with Spectre simulations using BSIM3v3 model, for a wide range of device sizes, capacitive loads, transition times, and aspect ratios (W/sub p//W/sub n/). Since this model is independent of extracted and fitting parameters, it is technology portable. The model is validated for three DSM technologies (UMCs 0.13 /spl mu/m, and TSMCs 0.18 /spl mu/m and 0.25 /spl mu/m). For all, the model shows good accuracy with on average error of about 4%. The maximum error is less than 10%.

Mapping the AWE-RLC model into a simple RC circuit with its application to buffer insertion

GAM, TPN and AWE methods have been accepted by many researchers as methods of modeling on-chip interconnects as RC, and RLC circuits. In this paper a platform to generate the T and Π configurations for RC, RLC and RLCG models based on GAM, TPN and AWE methods is proposed. With the Π configuration of AWE-based RLC model provides the best performance, this model has been mapped to an equivalent simple RC model. This improved RC model has been utilized for buffer insertion, which caused interconnect delay to be reduced and the number of buffers and their sizes to be lowered.

FPGA implementation of adaptive segmentation for non-stationary biomedical signals

A novel field programmable gate array (FPGA) implementation of adaptive segmentation for non-stationary biomedical signals is presented. The design uses Simulink-to-FPGA methodology and has been successfully implemented onto Xilinx Virtex II Pro device. The implementation is based on the recursive least-squares lattice (RLSL) algorithm using double-precision floating-point arithmetic and is programmable for users providing data length, system order and threshold selection functions. The implemented RLSL design provides very good performance in obtaining accurate conversion factor values with a mean correlation above 99% and detecting segment boundaries with high accuracy for both synthesised and real-world biomedical signals.