Dhamin Al-Khalili

Comparison of 32-bit multipliers for various performance measures

Comparison of five different 32-bit integer multipliers is done for various performance measures. Multipliers included in comparison are the array multiplier, modified Booth (radix-4) multiplier, optimized Wallace tree multiplier, combined modified Booth-Wallace tree multiplier and twin pipe serial parallel multiplier. Comparison is based on synthesis results obtained by synthesizing all multiplier architectures towards FPGA.

A module generator for optimized CMOS buffers

The theory and implementation of a module generator for CMOS buffers are presented. The generator is written in the C language, and outputs optimal buffer designs in respect to a preselected objective function and layout. The user has the choice of minimizing delay, power, and area, or a combination of these, plus the choice of layout configuration. The research concentrates mainly on theoretical analysis, where variations of process, design, and layout parameters with respect to each objective function are studied in detail. >

Delay analysis of CMOS gates using modified logical effort model

In this paper, modified logical effort (MLE) technique is proposed to provide delay estimation for CMOS gates. The model accounts for the behavior of series-connected MOSFET structure (SCMS), the input transition time, and internodal charges. Also, the model takes into account deep submicron effects, such as mobility degradation and velocity saturation. This model exhibits good accuracy when compared with Spectre simulations based on BSIM3v3 model. Using UMCs 0.13-/spl mu/m and TSMCs 0.18-/spl mu/m technologies, the model has an average error of 4.5% and a maximum error of 15%.

Technology-portable analytical model for DSM CMOS inverter transition-time estimation

In this paper, we propose a new analytical model to estimate the transition time of CMOS inverters. Accounting for the main effects of deep sub-micron such as velocity saturation and mobility degradation, the relationship between the input and output transition is discussed and captured by a closed-form expression. The developed model has been formulated to depend only on device model parameters, which are usually provided with the given technology. The proposed model was verified against circuit simulation using Spectre level 11 (BSIM3v3) for a wide range of transistor sizes, output loading and input transition times. It has also been tested for portability between 0.25 /spl mu/m, 0.18 /spl mu/m and 0.13 /spl mu/m technologies Our model showed good accuracy compared to simulation with maximum error of 10% and an average error of 4%.

Optimised realisations of large integer multipliers and squarers using embedded blocks

An efficient design methodology and a systematic approach for the implementation of multiplication and squaring functions for unsigned large integers, using small-size embedded multipliers are presented. A general architecture of the multiplier and squarer is proposed and a set of equations is derived to aid in the realisation. The inputs of the multiplier and squarer are split into several segments leading to an efficient utilisation of the small-size embedded multipliers and a reduced number of required addition operations. Various benchmarks were tested for different segments ranging from 2 to 5 targeting Xilinx Spartan-3 FPGAs. The synthesis was performed with the aid of the Xilinx ISE 7.1 XST tool. The approach was compared with the traditional technique using the same tool. The results illustrate that the design approach is very efficient in terms of both timing and area savings. Combinational delay is reduced by an average of 7.71% for the multiplier and 21.73% for the squarer. In terms of 4-inputs look-up tables, area is lowered by an average of 11.63% for the multiplier and 52.22% for the squarer. In the case of the multiplier, both approaches use the same number of embedded multipliers. For the squarer, the proposed approach reduces the number of required embedded multipliers by an average of 32.77% compared with the traditional technique.

A Module Generator for Optimized CMOS Buffers

A module generator for CMOS buffers have been written in C. The generator optimizes buffer design with respect to a user specified objective function both in terms of performance and layout. Speed, area, power consumption, power-delay, AT and AT/sup 2/ are selectively optimized before the layout is produced. Such layout is generated in various configurations depending on load size. Technology file is easily updatable.

UDSM subthreshold leakage model for NMOS transistor stacks

In this paper, a new, analytical model for subthreshold leakage estimation in the ultra deep submicron (UDSM) realm is proposed. Most previous attempts at subthreshold leakage estimation in transistor stacks are not tailored for the UDSM realm and are based on either a look up table approach, and/or assume that all the transistors in the stack have a fixed width. The analytical estimation model proposed in this paper is capable of estimating subthreshold leakage in UDSM NMOS transistor stacks with different transistor widths. The model achieves this by estimating the stack nodal voltages. In this paper, transistor stacks of two, three and four transistors are considered. Compared to SPICE simulations using PTMs BSIM4 models, our analytical model achieved an average error of 8.1% for the one, two, three and four transistor stacks for 65, 45 and 32nm CMOS process technologies. The model also exhibits significant runtime savings when compared with SPICE.

Optimized realization of large-size two’s complement multipliers on FPGAs

This paper presents an optimized design approach of twos complement large-size multipliers using embedded multipliers in FPGAs. The realization is based on Baugh-Wooleys algorithm. To achieve efficient implementation, a set of optimized schemes for the realization of the addition of partial products is proposed. The implementations of the multipliers have been carried out for operands with sizes from 20 to 128 bits. The results indicate that our proposed approach outperforms the traditional methods by as high as 50% in terms of LUT-delay product.

Accurate Total Static Leakage Current Estimation in Transistor Stacks

In this paper, a simple model for the estimation of static leakage current in NMOS transistor stacks is introduced. The three leakage mechanisms addressed are subthreshold leakage, gate-tunneling and gate induced drain leakage (GIDL). The algorithmic description of the model can be broken down into three phases i) pre-extraction , ii) estimation and iii) width scaling. In the pre-extraction phase, data necessary for subthreshold leakage estimation is extracted a priori. This also involves characterizing voltages required for a specific set of input vector scenarios (exception vectors/voltages). In the estimation phase, unit width GIDL and gate tunneling are estimated deterministically while subthreshold leakage is estimated using the pre-extracted data. Finally, in the width scaling phase each leakage component is then width scaled and summed, to give the total static leakage exhibited by the stack. The proposed model was scripted in MatLab and compared with SPICE simulations for various scenarios. The average total error for each scenario was under 3%.

Efficient Realization of Large Integer Multipliers and Squarers

This paper presents an efficient design methodology and a systematic approach for the implementation of multiplication and squaring function for large integers using small-size embedded multipliers. A general architecture of the multiplier and squarer is proposed as well as a set of equations is derived to aid in the realization. The inputs of the multiplier and squarer are split into several segments leading to an efficient utilization of the small-size embedded multipliers and a reduced number of required addition operations. Various benchmarks were tested for different segments ranging from 2 to 4 targeting Xilinx Spartan-3 FPGA. The synthesis was performed with the aid of the Xilinx ISE 7.1 XST tool. Our approach was compared with the traditional technique using the same tool. The results illustrate that our design approach is very efficient in terms of both timing and area saving. The combinational delay is reduced by an average of 6.1% for the multiplier and 15.5% for the squarer. The area saving, in terms of number of 4-input LUTs, is about 8.3% for the multiplier and 50% for the squarer. In the case of the multiplier, both the approaches use the same number of embedded multipliers. For the squarer, our proposed approach has reduced the number of required embedded multipliers by an average of 30.5% compared to the traditional technique