Kostas Siozios

A Heterogeneous Multicore System on Chip with Run-Time Reconfigurable Virtual FPGA Architecture

System design, especially for low power embedded applications often profit from a heterogeneous target hardware platform. The application can be partitioned into modules with specific requirements e.g. parallelism or performance in relation to the provided hardware blocks on the multicore hardware. The result is an optimized application mapping and a parallel processing with lower power consumption on the different cores on the hardware. This paper presents a heterogeneous platform consisting of a microprocessor and a field programmable gate array (FPGA) connected via a standard AMBA bus. The novelty of this approach is that the FPGA is realized as virtual reconfigurable hardware upon a traditional off the shelf FPGA device. The advantage with this approach is that the specification of the virtual FPGA stays unchanged, independent to the underlying hardware and provides therefore features, which the exploited physical host FPGA cannot provide. A special feature of the presented virtual FPGA amongst others is the dynamic reconfigurability which is for example not available with all off the shelf FPGAs. Furthermore the concept of FPGA virtualization enables the re-use of hardware blocks on other physical FPGA devices. This paper presents the hardware platform and describes the tool chain for the heterogeneous system on chip.

Architecture-Level Exploration of Alternative Interconnection Schemes Targeting 3D FPGAs: A Software-Supported Methodology

In current reconfigurable architectures, the interconnection structures increasingly contribute more to the delay and power consumption. The demand for increased clock frequencies and logic density (smaller area footprint) makes the problem even more important. Three-dimensional (3D) architectures are able to alleviate this problem by accommodating a number of functional layers, each of which might be fabricated in different technology. However, the benefits of such integration technology have not been sufficiently explored yet. In this paper, we propose a software-supported methodology for exploring and evaluating alternative interconnection schemes for 3D FPGAs. In order to support the proposed methodology, three new CAD tools were developed (part of the 3D MEANDER Design Framework). During our exploration, we study the impact of vertical interconnection between functional layers in a number of design parameters. More specifically, the average gains in operation frequency, power consumption, and wirelength are 35%, 32%, and 13%, respectively, compared to existing 2D FPGAs with identical logic resources. Also, we achieve higher utilization ratio for the vertical interconnections compared to existing approaches by 8% for designing 3D FPGAs, leading to cheaper and more reliable devices.

Designing 2D and 3D Network-on-Chip Architectures

This book covers key concepts in the design of 2D and 3D Network-on-Chip interconnect. It highlights design challenges and discusses fundamentals of NoC technology, including architectures, algorithms and tools. Coverage focuses on topology exploration for both 2D and 3D NoCs, routing algorithms, NoC router design, NoC-based system integration, verification and testing, and NoC reliability. Case studies are used to illuminate new design methodologies.

DAGGER: a novel generic methodology for FPGA bitstream generation and its software tool implementation

A novel bitstream generation algorithm and its software implementation are introduced. Although this tool was developed for the configuration of AMDREL FPGA reconfigurable platform, it could be used to program any other compatible device. This tool is the only one known academic implementation for FPGA configuration with such features. Among them are the run-time-, partial- and dynamic-reconfiguration, the memory management, the bitstream compression and encryption, the read-back technique, the bitstream reallocation, the used low-power techniques as well as the graphical user interface.

An integrated framework for architecture level exploration of reconfigurable platform

In this paper, the EX-VPR tool, which used for architecture level exploration, is presented. This tool belongs to an integrated framework (MEANDER) for mapping applications into a fine-grain reconfigurable platform (FPGA). Having as input VHDL description of an application, the framework produces the appropriate configuration bitstream. The proposed tool framework supports a variety of FPGA architectures. Additionally, a novel power aware switch box is proposed. Quantitative comparisons with existing switch boxes are provided, yielding promising results.

SPARTAN: Developing a Vision System for Future Autonomous Space Exploration Robots

Mars exploration is expected to remain a focus of the scientific community in the years to come. A Mars rover should be highly autonomous because communication between the rover and the terrestrial operation center is difficult, and because the vehicle should spend as much of its traverse time as possible moving. Autonomous behavior of the rover implies that the vision system provides both a wide view to enable navigation and three-dimensional (3D) reconstruction, and at the same time a close-up view ensuring safety and providing reliable odometry data. The European Space Agency funded project “SPAring Robotics Technologies for Autonomous Navigation” (SPARTAN) aimed to develop an efficient vision system to cover all such aspects of autonomous exploratory rovers. This paper presents the development of such a system, starting from the requirements up to the testing of the working prototype. The vision system was designed with the intention of being efficient, low-cost, and accurate and to be implemented using custom-designed vectorial processing by means of field programmable gate arrays (FPGAs). A prototype of the complete vision system was developed, mounted on a basic mobile robot platform, and tested. The results on both real-world Mars-like and long-range simulated data are presented in terms of 3D reconstruction and visual odometry accuracy, as well as execution speed. The developed system is found to fulfill the set requirements.

A novel framework for exploring 3-D FPGAs with heterogeneous interconnect fabric

A heterogeneous interconnect architecture can be a useful approach for the design of 3-D FPGAs. A methodology to investigate heterogeneous interconnection schemes for 3-D FPGAs under different 3-D fabrication technologies is proposed. Application of the proposed methodology on benchmark circuits demonstrates an improvement in delay, power consumption, and total wire-length of approximately 41%, 32%, and 36%, respectively, as compared to 2-D FPGAs. These improvements are additional to reducing the number of interlayer connections. The fewer interlayer connections are traded off for a higher yield. An area model to evaluate this trade-off is presented. Results indicate that a heterogeneous 3-D FPGA requires 37% less area as compared to a homogeneous 3-D FPGA. Consequently, the heterogeneous FPGAs can exhibit a higher manufacturing yield. A design toolset is also developed to support the design and exploration of various performance metrics for the proposed 3-D FPGAs.

A software-supported methodology for designing high-performance 3D FPGA architectures

A software-supported systematic methodology for exploring and evaluating alternative 3D reconfigurable FPGA architectures is introduced. Two new software tools were developed: (i) a placement and routing tool for 3D FPGAs (3DPRO) and (H) a power/energy consumption estimation tool for such architectures (3DPower). Both of them are part of the new Design Framework, named 3D-MEANDER. We mainly focus our exploration on parameters that dominate the maximum operation frequency of the 3D FPGAs (i.e. vertical interconnections, number of layers, etc.). We evaluate the efficiency of the proposed methodology by making an exhaustive exploration for device delay, power consumption and utilized number of vertical connections for alternative 3D interconnection schemes. Experimental results demonstrate the effectiveness of our methodology, considering the 20 largest MCNC benchmarks. We achieve an average decrease in the delay, the wire length, and the energy consumption of 27%, 26%, and 34%, respectively, as compared to traditional 2D FPGAs, considering 3D architectures with 50% and 70% of fabricated vias. Also, we proved that actually-utilized via links are practically independent from the number of fabricated vias of a 3D FPGA architecture.

On Supporting Efficient Partial Reconfiguration with Just-In-Time Compilation

Partial reconfiguration is possible to deliver virtually unlimited hardware resources since it enables dynamic allocation and de-allocation of tasks onto a reconfigurable architecture, while the rest tasks continue to operate. However, in order to benefit from this flexibility, partial reconfiguration has to be appropriately applied. Among others, the placement of partial configuration data is a critical issue since it affects the fragmentation of hardware resources. In this paper we introduce a novel methodology for supporting partial reconfiguration with the usage of a Just-in-Time (JIT) Compilation framework. Experimental results with a number of benchmarks showed that the introduced solution performs application P&R 7.34× faster, as compared to the state-of-the-art tools, while it also leads to significant lower fragmentation of hardware resources.

A Tabu-Based Partitioning and Layer Assignment Algorithm for 3-D FPGAs

Integrating more functionality in a smaller form factor with higher performance and lower power consumption is pushing semiconductor technology scaling to its limits. Three-dimensional (3-D) chip stacking is touted as the silver bullet technology that can keep Moores momentum and fuel the next wave of consumer electronics products. This letter introduces a TSV-aware partitioning algorithm that enables higher performance for application implementation onto 3-D field-programmable gate arrays (FPGAs). Unlike other algorithms that minimize the number of connections among layers, our solution leads to a more efficient utilization of the available (fabricated) interlayer connectivity. Experimental results show average reductions in delay and power consumption, as compared to similar 3-D computer-aided design (CAD) tools, about 28% and 26%, respectively.